Abstract: A first node includes a DMA engine for transferring data specified by a sequence of control blocks to a second node. When a control block does not require synchronization between memories, the DMA engine sends an end of transfer (EOT) message after the last datum, increments an EOT counter, and processes the next control block. When a control block requires synchronization and the EOT counter is at zero, the DMA engine sends an EOT with a flag after the last datum, increments the EOT counter, and waits for the EOT counter to return to zero before processing the next control block. A memory controller at the second node detects the EOT with or without a flag and generates an EOT acknowledgement with or without a flag. When a link interface at the second node detects the EOT acknowledgement with a flag, it sends an interrupt to a local processor complex.

Abstract: The uppermost metal layer (metal-one) on a flip-chip packageable IC is modified to include at least one VCC pad, at least one ground pad, and at least one and preferably five test pads. Each pad is sized to be probe wafer-contactable, is and electrically coupled to appropriate vias formed in the IC. During IC fabrication but before the destination layer is fabricated, the IC is tested using a wafer probe that couples appropriate signals and power to the pads formed on the metal-one layer. If testing discloses a bug, it is possible to modify the IC metal-one traces, e.g., using FIB and then re-wafer probe test the IC. An insulating layer and destination layer may then be fabricated over what is known to be a good IC, and re-testing may occur. In this fashion, debugging diagnostics are made using testable ICs, and any metal-one revision may be tried and confirmed before changing the metal-one pattern for mass produced ICs.