Abstract: A method of coordinating a mixed-reality (MR) configured head-mounted display (HMD) with a separate media device to enable a synchronized user experience. The method includes establishing a communication channel between the HMD and the media device. At least one of the following is performed via the communication channel: accessing content on the media device or executing control commands on the media device based on an interface displayed by the HMD, or detecting media content presented by the media device and synchronizing display of MR content on the HMD and the detected media content.

Abstract: A method of coordinating a mixed-reality (MR) configured head-mounted display (HMD) with a separate media device to enable a synchronized user experience. The method includes establishing a communication channel between the HMD and the media device. At least one of the following is performed via the communication channel: accessing content on the media device or executing control commands on the media device based on an interface displayed by the HMD, or detecting media content presented by the media device and synchronizing display of MR content on the HMD and the detected media content.

Abstract: A technique for controlling the flow of among the ports of a multi-port bridge. The bridge includes a memory for storing packets and a plurality of ports. Each port includes a receive buffer, a transmit buffer and a “triplet” buffer. A data packet is received by the receive buffer of a port. As the packet is still being received, a look-up table is utilized to identify the appropriate destination port for the packet. A result of the look-up is a “triplet” which includes three fields: a first field containing the identification of the source port, a second field containing the identification of the destination port, and a third field containing a starting address assigned to the incoming packet in the memory. The triplet is placed upon the communication bus a first time. If the destination port is available to receive the packet directly from the source port, the destination port receives the packet simultaneously as the packet is stored in the memory.

Abstract: A single-chip, network interface controller (NIC) integrated circuit (IC) with a host interface and arbiter common to two 10BASE-T ETHERNET local area network (LAN) segments with respective unshielded twisted pair interfaces, encoder-decoders, medium access controllers, first-in first-out register memory arrays, and buffer management. Source-address and destination-address content addressable memories are connected to respective MAC receivers in the-medium access controllers to both learn the addresses of network clients on the two segments and then to transparently bridge packets between the LAN segments. The NIC effectively increases the bandwidth of a server connection to the thus unified network.

Abstract: A single-chip, network interface controller (NIC) integrated circuit (IC) with a host interface and arbiter common to two 10BASE-T ETHERNET local area network (LAN) segments with respective unshielded twisted pair interfaces, encoder-decoders, medium access controllers, first-in first-out register memory arrays, and buffer management. Source-address and destination-address content addressable memories are connected to respective MAC receivers in the medium access controllers to both learn the addresses of network clients on the two segments and then to transparently bridge packets between the LAN segments. The NIC effectively increases the bandwidth of a server connection to the thus unified network.

Abstract: A technique for periodically updating entries in a look-up table for directing data packets through a multi-port bridge in a local area network. For packets received during a first period, the number of the port receiving the packet is stored with the address of the node which generated the packet in a first memory and in a second memory. During the first period, the first memory is utilized for directing packets through the multi-port bridge. At the end of the first period, a third memory is cleared. For packets received during a second period, the number of the port receiving the packet is stored with the address of the node which generated the packet in the second memory and in the third memory. During the second period, the second memory is utilized for directing packets through the multi-port bridge. At the end of the second period, the first memory is cleared.

Abstract: A technique for controlling the flow of packets in a multi-port bridge according to availability of resources within the bridge. The bridge includes a memory for storing packets and a plurality of ports. Each port includes a receive buffer, a transmit buffer and a memory pointer buffer. A data packet is received by the receive buffer of a port. As the packet is still being received, a look-up table is utilized to determine which is the appropriate destination port for the packet. If the memory pointer buffer in the destination port is nearly full, the destination port generates a jam request. The source port receives the jam request and, in response, discards the incoming packet and sends a jam signal. Otherwise, the memory pointer is stored in the destination port until the packet can be retrieved from the memory for transmission by the destination port.

Abstract: A single-chip, network interface controller (NIC) integrated circuit (IC) with a host interface and arbiter common to two 10BASE-T ETHERNET local area network (LAN) segments with respective unshielded twisted pair interfaces, encoder-decoders, medium access controllers, first-in first-out register memory arrays, and buffer management. Source-address and destination-address content addressable memories are connected to respective MAC receivers in the medium access controllers to both learn the addresses of network clients on the two segments and then to transparently bridge packets between the LAN segments. The NIC effectively increases the bandwidth of a server connection to the thus unified network.

Abstract: A one-chip local area network (LAN) device comprises more than one local area network interface ports each including one receiver (11-14), one transmitter (15-18) and one triplet processor (25-28), a high-speed data bus (24) to which individual ones of the plurality of local area network interface ports are connected, and a switch engine (34) connected to the high-speed data bus (24) and including a packet buffer controller (40), a high-speed data bus controller (42) and content-addressable memory manager (44). Each triplet processor (25-28), provides for the reading of a destination address in packets received from a corresponding one of the local area network interface ports and simultaneously provides for the cut-through transmission of packets received from other ones of the local area network interface ports that transfer the packets over the high-speed data bus (24).

Abstract: A method and apparatus for encoding and decoding digital information upon a recording medium using the time interval between adjacent pairs of pulses. A number "n" of unique time intervals between pulse pairs correspond to "n" unique symbols contained within a coding table. Assignment of the durations between pulses adapted to the frequency of occurrence of particular symbols within a data stream materially increases the efficiency of the method. Division of the data stream and numerical transformation of the data stream improve the efficiency of adaptive assignment of the durations between pulses on the basis of frequency of occurrence of particular symbols within a data stream. The method realizes a multiple-fold increase in data storage capacity of rotating magnetic disk memories over common MFM encoding, and the method similarly realizes a multiple-fold increase in data transfer rate for telecommunications applications.

Abstract: A method and apparatus are described for generating, under the control of a microprocessor, signals for operating a scanning system of a standard television receiver. A plurality of display segments, each containing information at least partially defining one or more object images that may be desired be included in a specified display on the receiver, are stored in a cartridge memory which can also include specific operating instructions for carrying out a particular video game or other function with such display segments. Indicia uniquely associated with each of the display segments are placed in a predetermined order correlated with the order of appearance in the display of those display seqments which are to be included therein.

Abstract: A method and apparatus for generating, under the control of a microprocessor, signals for operating a visual display mechanism of the scanning type. The position of the scan is tracked, and when it approaches a desired location on the display area for a particular segment to be displayed, it responds thereto by directing delivery to the scanning system of control signals which define the selected display segment. A plurality of display segments, each containing information at least partially defining one or more object images which it may be desired to be included in a specified display, are stored in a cartridge memory which can also include specific operating instructions for carrying out a particular game or other function with such display segments. Each of the display composers includes an associative memory arrangement for addressing the cartridge memory and directing feedout therefrom of specified segments at times required during the scan.

Abstract: A method and apparatus is described for applying a video composite signal to the antenna input of a television receiver while at the same time electrically isolating such input from the equipment which generates the composite signal. The method includes the step of connecting to the antenna input a modulator for the composite signal having an optical sensor at its input for receiving optical radiation defining the composite signal, and converting the same into an electrical signal providing information to the modulator defining such composite signal. It further includes transmitting to the optical sensor optical radiation defining the desired composite signal.

Abstract: A microprocessor system having at least two separate scale integration devices. A first of the two large scale integration devices is a central processing unit formed on a single semiconductor die, and the second large scale integration device is a memory circuit formed on a separate single semiconductor die. The term "die" as used herein is conventional and refers to a unitary semiconductor body or chip. The central processing unit requires an external program counter which contains memory addresses of instruction codes to be used by the central processing unit. The memory device is electrically coupled to the central processing unit and includes a memory for storing the instruction codes, and a program counter for addressing the memory. Provision is made to incorporate additional memory circuits to expand the size and capability of the microprocessor system. System interrupt circuitry is also provided for interrupting system operation to change to a new sequence of instruction codes.

Abstract: A microprocessor system having at least two separate large scale integration devices. A first of the two large scale integration devices is a central processing unit formed on a single semiconductor die, and the second large scale integration device is a memory circuit formed on a separate single semiconductor die. The term "die" as used herein is conventional and refers to a unitary semiconductor body or chip. The central processing unit requires an external program counter which contains memory addresses of instruction codes to be used by the central processing unit. The memory device is electrically coupled to the central processing unit and includes a memory for storing the instruction codes, and a program counter for addressing the memory. Provision is made to incorporate additional memory circuits to expand the size and capability of the microprocessor system. System interrupt circuitry is also provided for interrupting system operation to change to a new sequence of instruction codes.