Patents by Inventor David Hwang
David Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145625Abstract: A device including an activated p-type layer comprising a III-Nitride based Mg-doped layer grown by vapor phase deposition or a growth method different from MBE. The p-type layer is activated through a sidewall of the p-type layer after the removal of defects from the sidewall thereby increasing a hole concentration in the p-type layer. In one or more examples, the device includes an active region between a first n-type layer and the p-type layer; a second n-type layer on the p-type layer; and a tunnel junction between the second n-type layer and the p-type layer, and the activated p-type layer has a hole concentration characterized by a current density of at least 100 Amps per centimeter square flowing between the first n-type layer and the second n-type layer in response to a voltage of 4 volts or less applied across the first n-type layer and the second n-type layer.Type: ApplicationFiled: February 28, 2022Publication date: May 2, 2024Applicant: The Regents of the University of CaliforniaInventors: David Hwang, Matthew S. Wong, Shuji Nakamura
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Publication number: 20240130977Abstract: Methods of making orally available softgels includes pre-wetting a probiotic with an edible oil to produce a wetted supplement, wherein the edible oil is present in a range of 25% to 75% by weight of a total weight of the probiotic and edible oil, heating the wetted supplement to a temperature in a range of 35° C. to 40° C., blending the wetted supplement and a molten chocolate component together to produce a liquid fill material, encapsulating the liquid fill material in a softgel coating to produce an orally available softgel, and cooling the orally available softgel to have a softgel capsule shell comprising 5% to 15% by weight water. The fill material is a solid at room temperature in the cooled orally available softgel.Type: ApplicationFiled: December 29, 2023Publication date: April 25, 2024Applicant: Captek Softgel InternationalInventors: Timothy Brian Chiprich, Argelia Sinay Melendez, Bibu Philip George, David Wood, Jangsoon Park, Jung Ku Cho, Lilyan Hong Tran, Paul Hwang, Ronnie Bayless
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Publication number: 20240071773Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.Type: ApplicationFiled: August 11, 2023Publication date: February 29, 2024Applicant: Applied Materials, Inc.Inventors: Lei Liao, Yichuan Ling, Zhiyu Huang, Hideyuki Kanzawa, Fenglin Wang, Rajesh Prasad, Yung-Chen Lin, Chi-I Lang, Ho-yung David Hwang, Lequn Liu
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Publication number: 20240020114Abstract: The subject technology detects a code commit at a code repository. The subject technology sends a request for a build job to a build server. The subject technology determines that the build job is completed. The subject technology sends a training request and user token to a proxy authenticator. The subject technology determines determining that the user token is validated. The subject technology sends a training request and the user token to a training job manager. Further, the subject technology determines determining that the training job is completed.Type: ApplicationFiled: September 26, 2023Publication date: January 18, 2024Inventors: William STORY, David HWANG
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Patent number: 11869807Abstract: Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle.Type: GrantFiled: June 1, 2021Date of Patent: January 9, 2024Assignee: Applied Materials, Inc.Inventors: Lili Feng, Yuqiong Dai, Madhur Sachan, Regina Freed, Ho-yung David Hwang
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Publication number: 20230395560Abstract: This disclosure is related to integrating microdevices into a system substrate. In particular the microdevices are transferred from a donor substrate into a system backplane where the microdevices connection pads are adhered to a pads on the system substrate at a temperature that is below the melting point of the materials on the pads of the system substrate and microdevice pads. The present disclosure also relates to integrating vertical microdevices into a system substrate. The system substrate can have a backplane circuit as well. The integration covers the microdevices with dielectrics and couples the backplane through a VIA. The disclosure further relates to a method and structure of microdevice or optoelectronic devices that allows for misalignment adjustment. The microdevices comprise a stack of semiconductor layers that in configuration with electrodes, substrate, VIA's and size factors minimize misalignment.Type: ApplicationFiled: September 2, 2021Publication date: December 7, 2023Applicant: VueReal Inc.Inventors: Gholamreza CHAJI, Ehsanollah FATHI, Hossein Zamani SIBONI, Lauren LESERGENT, David HWANG, Pranav GAVIRNENI
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Publication number: 20230384680Abstract: A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.Type: ApplicationFiled: August 4, 2023Publication date: November 30, 2023Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
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Patent number: 11809863Abstract: The subject technology detects a code commit at a code repository. The subject technology sends a request for a build job to a build server. The subject technology determines that the build job is completed. The subject technology sends a training request and user token to a proxy authenticator. The subject technology determines determining that the user token is validated. The subject technology sends a training request and the user token to a training job manager. Further, the subject technology determines determining that the training job is completed.Type: GrantFiled: November 8, 2021Date of Patent: November 7, 2023Assignee: Stripe, Inc.Inventors: William Story, David Hwang
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Publication number: 20230260856Abstract: The present invention relates to the inspection process which includes providing access to the microdevice contacts, measuring the microdevice and analyzing the data to identify defects or performance of the micro device. The invention also relates to the forming of test electrodes on microdevices. The test electrodes may be connected to hidden contacts. The type of microdevices may be vertical, lateral or a flip chip.Type: ApplicationFiled: July 15, 2021Publication date: August 17, 2023Applicant: VueReal Inc.Inventors: Gholamreza CHAJI, Ehsanollah FATHI, Hossein Zamani SIBONI, David HWANG
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Publication number: 20230215735Abstract: A method of forming features over a semiconductor substrate is provided. The method includes supplying a gas mixture over a surface of a substrate at a continuous flow rate. A first radio frequency (RF) signal is delivered to an electrode while the gas mixture is supplied at the continuous flow rate to deposit a polymer layer over the surface of the substrate. The surface of the substrate includes an oxide containing portion and a nitride containing portion. A second RF signal is delivered to the electrode while continuously supplying the gas mixture at the continuous flow rate to selectively etch the oxide containing portion relative to the nitride containing portion.Type: ApplicationFiled: November 14, 2022Publication date: July 6, 2023Inventors: Lei LIAO, Yung-chen LIN, Chi-I LANG, Ho-yung David HWANG
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Patent number: 11677042Abstract: Disclosed herein are methods, systems, and apparatuses for an light emitting diode (LED) array apparatus. In some embodiments, the LED array apparatus may include a plurality of mesas etched from a layered epitaxial structure. The layered epitaxial structure may include a P-type doped semiconductor layer, a active layer, and an N-type doped semiconductor layer. The LED array apparatus may also include one or more regrowth semiconductor layers, including a first regrowth semiconductor layer, which may be grown epitaxially over etched facets of the plurality of mesas. In some cases, for each mesa, the first regrowth semiconductor layer may overlay etched facets of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer, around an entire perimeter of the mesa.Type: GrantFiled: March 29, 2020Date of Patent: June 13, 2023Assignee: META PLATFORMS TECHNOLOGIES, LLCInventors: Markus Broell, Michael Grundmann, David Hwang, Stephan Lutgen, Brian Matthew Mcskimming, Anurag Tyagi
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Patent number: 11638374Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.Type: GrantFiled: April 14, 2022Date of Patent: April 25, 2023Assignee: Applied Materials, Inc.Inventors: Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-yung David Hwang, Samuel E. Gottheim
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Patent number: 11581457Abstract: Disclosed herein are systems and methods for reducing surface recombination losses in micro-LEDs. In some embodiments, a method includes increasing a bandgap in an outer region of a semiconductor layer by implanting ions in the outer region of the semiconductor layer and subsequently annealing the outer region of the semiconductor layer to intermix the ions with atoms within the outer region of the semiconductor layer. The semiconductor layer includes an active light emitting layer. A light outcoupling surface of the semiconductor layer has a diameter that is less than twice an electron diffusion length of the semiconductor layer. The outer region of the semiconductor layer extends from an outer surface of the semiconductor layer to a central region of the semiconductor layer that is shaded by a mask during the implanting of the ions.Type: GrantFiled: April 27, 2021Date of Patent: February 14, 2023Assignee: Meta Platforms Technologies, LLCInventors: Thomas Lauermann, Stephan Lutgen, David Hwang
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Publication number: 20230045689Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Applicant: Applied Materials, Inc.Inventors: Hao Jiang, Chi Lu, He Ren, Chi-I Lang, Ho-yung David Hwang, Mehul Naik
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Patent number: 11508618Abstract: Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications.Type: GrantFiled: July 14, 2021Date of Patent: November 22, 2022Assignee: Applied Materials, Inc.Inventors: Yung-Chen Lin, Qingjun Zhou, Ying Zhang, Ho-yung David Hwang
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Patent number: 11508617Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.Type: GrantFiled: October 24, 2019Date of Patent: November 22, 2022Assignee: Applied Materials, Inc.Inventors: Hao Jiang, Chi Lu, He Ren, Chi-I Lang, Ho-yung David Hwang, Mehul Naik
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Publication number: 20220367186Abstract: Methods and film stacks for extreme ultraviolet (EUV) lithography are described. The film stack comprises a substrate with a hard mask, bottom layer, middle layer and photoresist. Etching of the photoresist is highly selective to the middle layer and a modification of the middle layer allows for a highly selective etch relative to the bottom layer.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Applicant: Applied Materials, Inc.Inventors: Nancy Fung, Chi-I Lang, Ho-yung David Hwang
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Publication number: 20220359289Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: Micromaterials LLCInventors: Regina Freed, Madhur Sachan, Susmit Singha Roy, Gabriela Alva, Ho-yung David Hwang, Uday Mitra, El Mehdi Bazizi, Angada Bangalore Sachid, He Ren, Sushant Mittal
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Patent number: 11495461Abstract: Methods for forming a film stack comprising a hardmask layer and etching such hardmask layer to form features in the film stack are provided. The methods described herein facilitate profile and dimension control of features through a proper profile management scheme formed in the film stack. In one or more embodiments, a method for etching a hardmask layer includes forming a hardmask layer on a substrate, where the hardmask layer contains a metal-containing material containing a metal element having an atomic number greater than 28, supplying an etching gas mixture to the substrate, and etching the hardmask layer exposed by a photoresist layer.Type: GrantFiled: February 25, 2020Date of Patent: November 8, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Tejinder Singh, Suketu Arun Parikh, Daniel Lee Diehl, Michael Anthony Stolfi, Jothilingam Ramalingam, Yong Cao, Lifan Yan, Chi-I Lang, Hoyung David Hwang
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Patent number: D1021228Type: GrantFiled: November 21, 2022Date of Patent: April 2, 2024Assignee: Pax Labs, Inc.Inventors: David Carlberg, Alexander Weiss, Alexander Ringrose, Devin Spratt, Marko Markovic, Robyn Nariyoshi, Brandon Cheung, Christopher Nicholas HibmaCronan, Joshua Morenstein, John Hwang