Abstract: Apparatus and methods to increase the range of a signal processing circuit. A system uses floating bias circuits coupled to a signal processing circuit to increase the range of power supplies that can be used with the signal processing circuit, while maintaining the components of the signal processing circuit within a breakdown voltage threshold. As the voltage level of the data signal varies, the voltage level of the floating bias circuits varies as well.

Abstract: Apparatus and methods to increase the range of a signal processing circuit. A system uses floating bias circuits coupled to a signal processing circuit to increase the range of power supplies that can be used with the signal processing circuit, while maintaining the components of the signal processing circuit within a breakdown voltage threshold. As the voltage level of the data signal varies, the voltage level of the floating bias circuits varies as well.

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Abstract: A multi-channel circuit includes a first-channel circuit configured to receive a digital input and a second-channel output voltage, and to generate a first-channel output voltage as a function of the received digital input and second-channel output voltage.

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Abstract: A circuit includes a pair of input transistors configured as a differential pair and having input terminals configured to receive an input voltage. The circuit also includes a first current source connected to and configured to provide a first tail current to the pair of input transistors, the first tail current being a class-A current having a non-zero quiescent value. The circuit also includes a second current source connected to and configured to provide a second tail current to the pair of input transistors, the second tail current being a class-B current having a zero quiescent value and a non-zero non-quiescent value. The second current source is configured to provide the second tail current as a function of the input voltage.

Abstract: A circuit includes a pair of input transistors configured as a differential pair and having input terminals configured to receive an input voltage. The circuit also includes a first current source connected to and configured to provide a first tail current to the pair of input transistors, the first tail current being a class-A current having a non-zero quiescent value. The circuit also includes a second current source connected to and configured to provide a second tail current to the pair of input transistors, the second tail current being a class-B current having a zero quiescent value and a non-zero non-quiescent value. The second current source is configured to provide the second tail current as a function of the input voltage.

Abstract: A multi-channel circuit includes a first-channel circuit configured to receive a digital input and a second-channel output voltage, and to generate a first-channel output voltage as a function of the received digital input and second-channel output voltage.

Abstract: A low quiescent power class AB current mirror circuit includes a first input transistor for receiving an input current and a second output transistor for providing an output current; the first and second transistors having bases connected together; and a first current supply for sinking current from the bases in response to a decrease in input current to lower the quiescent point of the transistors.

Abstract: A low quiescent power class AB current mirror circuit includes a first input transistor for receiving an input current and a second output transistor for providing an output current; the first and second transistors having bases connected together; and a first current supply for sinking current from the bases in response to a decrease in input current to lower the quiescent point of the transistors.

Abstract: A low quiescent power class AB current mirror circuit includes a first input transistor for receiving an input current and a second output transistor for providing an output current; the first and second transistors having bases connected together; and a first current supply for sinking current from the bases in response to a decrease in input current to lower the quiescent point of the transistors.

Abstract: A low quiescent power class AB current mirror circuit includes a first input transistor for receiving an input current and a second output transistor for providing an output current; the first and second transistors having bases connected together; and a first current supply for sinking current from the bases in response to a decrease in input current to lower the quiescent point of the transistors.