Patents by Inventor David Hogenmiller

David Hogenmiller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dividing and distributing the drive strength of a single clock buffer
    Patent number: 6819138
    Abstract: Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: November 16, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: David Hogenmiller, Harsh Sharma, Shervin Hojat
  • Use of coupling capacitance to balance skew in a network
    Patent number: 6789245
    Abstract: Coupling capacitance is used to balance skew in a network. In one embodiment, the coupling capacitance exerted by shielding wires oppositely adjacent one or more signal wires in a network is utilized to vary the speed of a signal carried on the one or more signal wires to balance skew in the network.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: September 7, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Shervin Hojat, David Hogenmiller, Harsh Sharma
  • Dividing and distributing the drive strength of a single clock buffer
    Publication number: 20040085094
    Abstract: Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer, to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.
    Type: Application
    Filed: November 4, 2002
    Publication date: May 6, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: David Hogenmiller, Harsh Sharma, Shervin Hojat
  • Template based clock routing and balancing
    Publication number: 20040078773
    Abstract: Predetermined and standardized path templates are introduced between points and/or elements in an integrated circuit layout. According to one embodiment of the invention, the standardized path templates are made up of two or more parallel tracks of path segments, with or without corresponding perpendicular path segments. According to the invention, the path segments are connected as needed to form serpentine or non-serpentine paths of the required length.
    Type: Application
    Filed: October 21, 2002
    Publication date: April 22, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: Harsh Sharma, Shervin Hojat, David Hogenmiller
  • Use of coupling capacitance to balance skew in a network
    Publication number: 20040068709
    Abstract: Coupling capacitance is used to balance skew in a network. In one embodiment, the coupling capacitance exerted by shielding wires oppositely adjacent one or more signal wires in a network is utilized to vary the speed of a signal carried on the one or more signal wires to balance skew in the network.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: Shervin Hojat, David Hogenmiller, Harsh Sharma