Patents by Inventor David Hugh McIntyre
David Hugh McIntyre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11011495Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.Type: GrantFiled: August 23, 2018Date of Patent: May 18, 2021Assignee: Advanced Micro Devices, Inc.Inventors: Milind Bhagavat, David Hugh McIntyre, Rahul Agarwal
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Publication number: 20200090736Abstract: A write driver includes a first write data driver, a second write driver, and a control circuit. The first (second) write data driver provides a true (complement) write data signal to an output thereof at a high voltage when a true (complement) data signal is in a first logic state, at a ground voltage when the true (complement) data signal is in a second logic state and a negative bit line enable signal is inactive, and at a voltage below the ground voltage when the true (complement) data signal is in the second logic state and the negative bit line enable signal is active. The control circuit provides the negative bit line enable signal in an active state when a power supply voltage is below a first threshold, and in an inactive state when the power supply voltage is above a second threshold higher than the first threshold.Type: ApplicationFiled: September 14, 2018Publication date: March 19, 2020Applicant: Advanced Micro Devices, Inc.Inventors: Alex Schaefer, Ravi Jotwani, David Hugh McIntyre
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Publication number: 20200066677Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.Type: ApplicationFiled: August 23, 2018Publication date: February 27, 2020Applicant: Advanced Micro Devices, Inc.Inventors: Milind Bhagavat, David Hugh McIntyre, Rahul Agarwal
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Patent number: 10366734Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.Type: GrantFiled: February 3, 2017Date of Patent: July 30, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Alexander W. Schaefer, Ravi T. Jotwani, Samiul Haque Khan, David Hugh McIntyre, Stephen Victor Kosonocky, John J. Wuu, Russell Schreiber
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Publication number: 20180226111Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.Type: ApplicationFiled: February 3, 2017Publication date: August 9, 2018Inventors: Alexander W. Schaefer, Ravi T. Jotwani, Samiul Haque Khan, David Hugh McIntyre, Stephen Victor Kosonocky, John J. Wuu, Russell Schreiber
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Patent number: 8788789Abstract: A method and an apparatus for power filtering in a Translation Look-aside Buffer (TLB) are described. In the method and apparatus, power consumption reduction is achieved by suppressing physical address (PA) reads from random access memory (RAM) if the previously translated linear address (LA), or virtual address (VA), is the same as the currently requested LA. To provide the correct translation, the output of the TLB is maintained if the previously translated LA and the LA currently requested for translation are the same.Type: GrantFiled: December 15, 2010Date of Patent: July 22, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Deepika Kapil, David Hugh McIntyre
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Patent number: 8683179Abstract: A method and a processor load/store unit (LSU) are described for performing store-to-load forwarding (STLF) from an interlocking store. STLF is performed when a starting address of the store and the load do not match, or when a data size of the store is smaller than a data size of the load. The LSU detects a load that interlocks with a store, and determines whether all or only a portion of data bytes needed by the load can be provided by the interlocking store. If it is determined that only a portion of the data bytes needed by the load can be provided by the interlocking store, then that portion of the data bytes is provided by a store data buffer (SDB) and the remaining portion of the data bytes needed by the load is provided by a data cache (DC). Otherwise, the SDB provides all of the data bytes.Type: GrantFiled: November 30, 2010Date of Patent: March 25, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Krishnan Ramani, Chitresh C. Narasimhaiah, David Hugh McIntyre
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Patent number: 8503210Abstract: A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.Type: GrantFiled: December 22, 2010Date of Patent: August 6, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Mandeep Singh, David Hugh McIntyre, Hung Phuong Ngo
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Patent number: 8374039Abstract: A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a condition that an equivalence signal indicates that read addresses for the first read port and the second read port are the same. The latching and multiplexing operation may be integrated. The memory cells may be 6-transistor synchronous random access memory (SRAM) cells, 8-transistor SRAM cells, or any type of memory cells.Type: GrantFiled: December 22, 2010Date of Patent: February 12, 2013Assignee: Advanced Micro Devices, Inc.Inventors: David Hugh McIntyre, Jimmy L. Reaves
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Publication number: 20120163102Abstract: A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a condition that an equivalence signal indicates that read addresses for the first read port and the second read port are the same. The latching and multiplexing operation may be integrated. The memory cells may be 6-transistor synchronous random access memory (SRAM) cells, 8-transistor SRAM cells, or any type of memory cells.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: David Hugh McIntyre, Jimmy L. Reaves
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Publication number: 20120163059Abstract: A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Mandeep Singh, David Hugh McIntyre, Hung Phuong Ngo
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Publication number: 20120159056Abstract: A method and an apparatus for power filtering in a Translation Look-aside Buffer (TLB) are described. In the method and apparatus, power consumption reduction is achieved by suppressing physical address (PA) reads from random access memory (RAM) if the previously translated linear address (LA), or virtual address (VA), is the same as the currently requested LA. To provide the correct translation, the output of the TLB is maintained if the previously translated LA and the LA currently requested for translation are the same.Type: ApplicationFiled: December 15, 2010Publication date: June 21, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Deepika Kapil, David Hugh McIntyre
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Publication number: 20120137109Abstract: A method and a processor load/store unit (LSU) are described for performing store-to-load forwarding (STLF) from an interlocking store. STLF is performed when a starting address of the store and the load do not match, or when a data size of the store is smaller than a data size of the load. The LSU detects a load that interlocks with a store, and determines whether all or only a portion of data bytes needed by the load can be provided by the interlocking store. If it is determined that only a portion of the data bytes needed by the load can be provided by the interlocking store, then that portion of the data bytes is provided by a store data buffer (SDB) and the remaining portion of the data bytes needed by the load is provided by a data cache (DC). Otherwise, the SDB provides all of the data bytes.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Krishnan Ramani, Chitresh C. Narasimhaiah, David Hugh McIntyre
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Patent number: 7215175Abstract: An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one embodiment of the present invention, a two-stage sensing scheme is implemented. The improved fuse sensing circuit uses current-mode sensing and implements an auto-read current reduction scheme. Using a level-detect circuit, the virtual ground is raised automatically if the high-voltage power supply exceeds core supply (Vdd) by a fixed dc voltage. This reduces effective sensing voltage and the read current and thus helps preserve unblown fuse integrity. In one embodiment of the invention, four modes of operation are implemented: “Normal Read,” “Unblown_Read,” “Blown_Read_1” and “Blown_Read_2.” The default read mode is the “normal read” while the “Unblown” and “Blown” read modes are for fuse calibration purposes.Type: GrantFiled: September 1, 2004Date of Patent: May 8, 2007Assignee: Sun Microsystems, Inc.Inventors: Gurupada Mandal, Suresh Seshadri, David Hugh McIntyre, Raymond A. Heald, William Y. Mo
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Patent number: 5831302Abstract: The voltage reference circuit is provided particularly but not exclusively for use in flash EPROM chips. The reference circuit is intended to be inhibited until proper start-up conditions have been established to allow the reference circuit to operate properly. This is achieved by incorporating an enable signal generating circuit which is responsive to start-up circuitry for generating an enable signal at an appropriate signal level.Type: GrantFiled: November 15, 1995Date of Patent: November 3, 1998Assignee: SGS-Thomson Microelectronics LimitedInventor: David Hugh McIntyre
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Patent number: 5652721Abstract: An integrated circuit device has a set of storage elements which are not reprogrammable or which are slow to reprogram and, associated with each storage element, a latch. With each storage element and latch there is associated a switch circuit which can either be connected to supply as an output a signal from the storage element or from the latch. In a test mode, the latches hold test data bits for testing the device and the switch circuits are operated to supply control signals from the test data bits. In a normal mode, the switch circuits are operated to supply control signals from the storage elements. The integrated circuit device includes functional circuitry which takes the form of programming circuitry for programming the storage elements responsive to the control signals.Type: GrantFiled: August 21, 1995Date of Patent: July 29, 1997Assignee: SGS-Thomson Microelectronics LimitedInventor: David Hugh McIntyre