Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.

Abstract: Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuitry for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (IO) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuity for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

Abstract: Examples of systems and methods described herein provide for erasing an encrypted key used for data access to a non-volatile memory device. A memory controller may generate an encrypted key for data access to non-volatile memory devices; and, to provide security of data stored on the non-volatile memory devices, the memory controller may store the encrypted key in a local cache of the memory controller. The encrypted key may be erased responsive to losing power or powering down of memory controller. Advantageously, the data stored at the non-volatile memory device may not be accessed when the memory controller (or a computing device implementing the memory controller) loses power. Accordingly, if a malicious actor were to physically remove (or steal) a computing device implementing the memory controller (e.g., a laptop computer), in an attempt to acquire the data, the data stored on the non-volatile memory devices could not be accessed.

Abstract: Examples of systems and method described herein or generating, in a memory controller and/or memory device, access codes for memory regions of the memory device using authentication logic, and for accessing the memory device using the access codes. For example, a memory controller and/or a coupled memory device may generate access codes that a host computing device may include in a memory access request to access one or more memory regions of the memory device. Data read or written at the memory device may in some examples only be accessed in accordance with the access codes for memory regions of the memory device. Accordingly, the systems and methods described herein may provide security for specific memory regions of a memory device because the access code are updated periodically (e.g., based on obtained reset indication) or in accordance with an updated count value from a counter.

Abstract: Methods, apparatuses, and systems for implementing data flows in a processor are described herein. A data flow manager may be configured to generate a configuration packet for a compute operation based on status information regarding multiple processing elements of the processor. Accordingly, multiple processing elements of a processor may concurrently process data flows based on the configuration packet. For example, the multiple processing elements may implement a mapping of processing elements to memory, while also implementing identified paths, through the processor, for the data flows. After executing the compute operation at certain processing elements of the processor, the processing results may be provided. In speech signal processing operations, the processing results may be compared to phonemes to identify such components of human speech in the processing results.

Abstract: Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (I/O) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.

Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory die. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices. Such devices can generate a Hamming processing command, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed on a memory die itself, like a memory die of a NAND memory device.

Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory controller with various memory devices. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at the memory controller coupled to memory devices.

Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.

Abstract: Methods, apparatuses, and systems for implementing data flows in a processor are described herein. A data flow manager may be configured to generate a configuration packet for a compute operation based on status information regarding multiple processing elements of the processor. Accordingly, multiple processing elements of a processor may concurrently process data flows based on the configuration packet. For example, the multiple processing elements may implement a mapping of processing elements to memory, while also implementing identified paths, through the processor, for the data flows. After executing the compute operation at certain processing elements of the processor, the processing results may be provided. In speech signal processing operations, the processing results may be compared to phonemes to identify such components of human speech in the processing results.

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

Abstract: A device comprising a plurality of antennas operable to transmit and receive communication packets via a plurality of communication protocols and an integrated circuit chip coupled to the plurality of antennas. The integrated circuit chip comprises a first and a second plurality of processing elements. The first plurality of processing elements operable to receive communication packets via a first one of a plurality of communication protocols and process an optimal route. The second plurality of processing elements communicatively coupled to the first plurality of processing elements and operable to determine the optimal route to transmit the communication packets from a source device to a destination device based, at least in part, on transmission characteristics associated with at least one of the source or destination devices.

Abstract: An apparatus, and a method therefore, are described, the apparatus according to one embodiment including a security manager and a plurality of clusters of processing elements. Each cluster of the plurality of clusters includes a respective plurality of processing elements. A controller of the apparatus, which may include a security manager, may be configured to control the plurality of clusters to receive a first data stream and a second data stream, control a first plurality of processing elements in a first cluster to process the first data stream using a first security protocol, and control a second plurality of processing elements in a second cluster to process the second data stream using a second security protocol.

Abstract: A device comprising a plurality of antennas operable to transmit and receive communication packets via a plurality of communication protocols and an integrated circuit chip coupled to the plurality of antennas. The integrated circuit chip comprises a first and a second plurality of processing elements. The first plurality of processing elements operable to receive communication packets via a first one of a plurality of communication protocols and process an optimal route. The second plurality of processing elements communicatively coupled to the first plurality of processing elements and operable to determine the optimal route to transmit the communication packets from a source device to a destination device based, at least in part, on transmission characteristics associated with at least one of the source or destination devices.