Patents by Inventor David Iezzi
David Iezzi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7885116Abstract: A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.Type: GrantFiled: February 9, 2009Date of Patent: February 8, 2011Inventors: Marco Pasotti, Guido De Sandre, David Iezzi, Marco Poles
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Publication number: 20090154249Abstract: A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.Type: ApplicationFiled: February 9, 2009Publication date: June 18, 2009Inventors: Marco Pasotti, Guido De Sandre, David Iezzi, Marco Poles
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Patent number: 7508716Abstract: A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.Type: GrantFiled: February 12, 2004Date of Patent: March 24, 2009Inventors: Marco Pasotti, Guido De Sandre, David Iezzi, Marco Poles
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Patent number: 7088614Abstract: A programming method of a multilevel memory cell is able to store a plurality of bits in a plurality of levels. The method includes writing a logic value in the multilevel memory cell by setting one of the programming levels thereof, these levels being included in the plurality of levels, with respect to a reference level according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value for the levels is reached. A multilevel memory device includes a plurality of multilevel memory cells organized into sectors, split into a plurality of data units whereon a programming operation is performed in parallel.Type: GrantFiled: December 26, 2002Date of Patent: August 8, 2006Assignee: STMicroelectronics S.r.l.Inventors: Guido De Sandre, Marco Poles, David Iezzi, Marco Pasotti
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Patent number: 6897710Abstract: An architecture for distributing supply voltages to a plurality of memory modules supplied through a plurality of charge pump circuits may include a sorting block bi-directionally connected to the plurality of memory modules, from which it may receive a plurality of power requests. The sorting block may provide a sorting signal based upon a priority scale to drive the plurality of charge pump circuits and distribute supply voltages to the plurality of memory modules. The architecture may advantageously be software-configurable.Type: GrantFiled: December 30, 2003Date of Patent: May 24, 2005Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Guido De Sandre, David Iezzi, Gilberto Muzzi, Marco Poles
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Publication number: 20040228162Abstract: A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.Type: ApplicationFiled: February 12, 2004Publication date: November 18, 2004Inventors: Marco Pasotti, Guido De Sandre, David Iezzi, Marco Poles
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Publication number: 20040201414Abstract: An architecture for distributing supply voltages to a plurality of memory modules supplied through a plurality of charge pump circuits may include a sorting block bi-directionally connected to the plurality of memory modules, from which it may receive a plurality of power requests. The sorting block may provide a sorting signal based upon a priority scale to drive the plurality of charge pump circuits and distribute supply voltages to the plurality of memory modules. The architecture may advantageously be software-configurable.Type: ApplicationFiled: December 30, 2003Publication date: October 14, 2004Applicant: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Guido De Sandre, David Iezzi, Gilberto Muzzi, Marco Poles
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Patent number: 6687159Abstract: A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.Type: GrantFiled: December 19, 2001Date of Patent: February 3, 2004Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Giovanni Guaitini, Guido De Sandre, David Iezzi, Marco Poles, Pierluigi Rolandi
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Patent number: 6687167Abstract: A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.Type: GrantFiled: August 20, 2002Date of Patent: February 3, 2004Assignee: STMicroelectronics S.r.l.Inventors: Giovanni Guaitini, Marco Pasotti, Guido De Sandre, David Iezzi, Marco Poles, Pier Luigi Rolandi
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Patent number: 6667903Abstract: It is described a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels. The method comprises the phases of: initially programming a cell threshold value to a first set of levels [0;(m−1)] being m a submultiple of the plurality of levels of the multilevel cell; reprogramming without erasing another set of levels [m;(2m−1)] containing the same number m of levels as the first set; reiterating the reprogramming without erasing phase until the levels of the multilevel cell are exhausted. It is also described a multilevel memory device of the type comprising a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units wherein a data updating operation is performed in parallel, the data units being programmed by means of the programming method.Type: GrantFiled: December 14, 2001Date of Patent: December 23, 2003Assignee: STMicroelectronics S.r.l.Inventors: Guido De Sandre, Marco Pasotti, Pier Luigi Rolandi, Giovani Guaitini, David Iezzi, Marco Poles
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Patent number: 6655758Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.Type: GrantFiled: December 19, 2001Date of Patent: December 2, 2003Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Guido De Sandre, Giovanni Guaitini, David Iezzi, Marco Poles, PierLuigi Rolandi
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Publication number: 20030159014Abstract: A programming method of a multilevel memory cell is able to store a plurality of bits in a plurality of levels. The method includes writing a logic value in the multilevel memory cell by setting one of the programming levels thereof, these levels being included in the plurality of levels, with respect to a reference level according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value for the levels is reached. A multilevel memory device includes a plurality of multilevel memory cells organized into sectors, split into a plurality of data units whereon a programming operation is performed in parallel.Type: ApplicationFiled: December 26, 2002Publication date: August 21, 2003Applicant: STMicroelectronics S.r.l.Inventors: Guido De Sandre, Marco Poles, David Iezzi, Marco Pasotti
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Publication number: 20030067804Abstract: The memory comprises a cell matrix, row decoder logic units, level conversion units (LSHx,y) and interface logic stages (ILOG) between the level conversion units and the row lines (WL) of the matrix. Each interface stage comprises elementary row driving stages, each with inputs (LXP, LYP) connected to the level conversion units (LSHx,y), an output connected to a row line (WL) and two supply terminals (SUPPLY_P, SUPPLY_N). Each elementary stage has an upper branch with a p-channel MOS transistor (P01) and a lower branch with an n-channel MOS transistor (N01). In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor (N00) in the upper branch and a p-channel transistor (P00) in the lower branch.Type: ApplicationFiled: August 20, 2002Publication date: April 10, 2003Inventors: Giovanni Guaitini, Marco Pasotti, Guido De Sandre, David Iezzi, Marco Poles, Pier Luigi Rolandi
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Patent number: 6535428Abstract: A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.Type: GrantFiled: June 14, 2001Date of Patent: March 18, 2003Assignee: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Guido De Sandre, Giovanni Guaitini, David Iezzi, Marco Poles, Michele Quarantelli, Pier Luigi Rolandi
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Publication number: 20020196664Abstract: A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.Type: ApplicationFiled: June 14, 2001Publication date: December 26, 2002Inventors: Marco Pasotti, Guido De Sandre, Giovanni Guaitini, David Iezzi, Marco Poles, Michele Quarantelli, Pier Luigi Rolandi
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Publication number: 20020149963Abstract: It is described a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels. The method comprises the phases of: initially programming a cell threshold value to a first set of levels [0;(m−1)] being m a submultiple of the plurality of levels of the multilevel cell; reprogramming without erasing another set of levels [m;(2m−1)] containing the same number m of levels as the first set; reiterating the reprogramming without erasing phase until the levels of the multilevel cell are exhausted. It is also described a multilevel memory device of the type comprising a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units wherein a data updating operation is performed in parallel, the data units being programmed by means of the programming method.Type: ApplicationFiled: December 14, 2001Publication date: October 17, 2002Applicant: STMicroelectronics S.r.l.Inventors: Guido De Sandre, Marco Pasotti, Pier Luigi Rolandi, Giovani Guaitini, David Iezzi, Marco Poles
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Publication number: 20020118573Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.Type: ApplicationFiled: December 19, 2001Publication date: August 29, 2002Applicant: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Guido De Sandre, Giovanni Guaitini, David Iezzi, Marco Poles, PierLuigi Rolandi
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Publication number: 20020105835Abstract: A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.Type: ApplicationFiled: December 19, 2001Publication date: August 8, 2002Applicant: STMicroelectronics S.r.l.Inventors: Marco Pasotti, Giovanni Guaitini, Guido De Sandre, David Iezzi, Marco Poles, Pierluigi Rolandi
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Patent number: 6123474Abstract: A selective call receiver assembly (10) comprises a front housing (14) having a plurality of apertures (15 & 16) and a multiplanar functional keypad (20), wherein the keypad has a first set of keys (23) and a second set of keys (22) residing on a first plane (30) and a third set of keys (21) residing on a second plane (28), the first, second, and third set of keys being integrally formed on one keypad and at least a portion of the first and third set of keys protruding through the plurality of apertures of the front housing when mounted within the front housing.Type: GrantFiled: March 8, 1996Date of Patent: September 26, 2000Assignee: Motorola, Inc.Inventors: Stephen M. Stanton, James Talmage Davis, II, Peter David Iezzi
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Patent number: D379987Type: GrantFiled: November 6, 1995Date of Patent: June 17, 1997Assignee: Motorola, Inc.Inventors: William Joseph Scheid, James Talmage Davis, II, Peter David Iezzi, Son Le