Patents by Inventor David J. Fensore

David J. Fensore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7877529
    Abstract: Synchronization management is provided for a continuous serial data streaming application wherein the serial data stream includes a plurality of consecutive, identical-length segments of consecutive serial data bits. Synchronization management bits are provided in each segment. The synchronization management bits are programmed such that the synchronization management bits contained in first and second adjacent segments of the serial data stream will bear a predetermined relationship to one another. At the receiving end, the synchronization management bits are examined from segment to segment. In this manner, synchronization can be monitored, synchronization loss can be detected, and synchronization recovery can be achieved.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: January 25, 2011
    Assignee: National Semiconductor Corporation
    Inventors: David J. Fensore, Robert L. Macomber, James E. Schuessler
  • Patent number: 7683673
    Abstract: Differential signal transmission circuitry in which multiple differential signal transmission circuits are coupled in a stacked relationship between the power supply electrodes to minimize power dissipation by reusing the signal currents among the channels.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: March 23, 2010
    Assignee: National Semiconductor Corporation
    Inventors: David J. Fensore, Alexander A. Alexeyev
  • Patent number: 7519789
    Abstract: A method for dynamically selecting a clock edge for recovering read data received from a slave at a master is provided that includes determining whether an internal clock signal is high when a first bit of read data is received at the master. One of a falling edge and a rising edge of the internal clock signal are selected for recovering the read data based on the determination of whether the internal clock signal is high when the first bit of read data is received at the master.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: April 14, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Robert L. Macomber, David J. Fensore
  • Patent number: 7509464
    Abstract: A system includes a memory operable to store scrambled data at a plurality of memory locations. The system also includes an empty detector operable to determine whether a specified memory location is empty using contents of the specified memory location. The contents of the specified memory location are not descrambled for use by the empty detector in determining whether the specified memory location is empty.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: March 24, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lawrence D. Getzin, David J. Fensore
  • Publication number: 20080266463
    Abstract: Differential signal transmission circuitry in which multiple differential signal transmission circuits are coupled in a stacked relationship between the power supply electrodes to minimize power dissipation by reusing the signal currents among the channels.
    Type: Application
    Filed: May 24, 2007
    Publication date: October 30, 2008
    Applicant: National Semiconductor Corporation
    Inventors: David J. Fensore, Alexander A. Alexeyev
  • Patent number: 7103734
    Abstract: A system includes a memory operable to store scrambled data at a plurality of memory locations. The system also includes an empty detector operable to determine whether a specified memory location is empty using contents of the specified memory location. The contents of the specified memory location are not descrambled for use by the empty detector in determining whether the specified memory location is empty.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: September 5, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lawrence D. Getzin, David J. Fensore
  • Patent number: 7035983
    Abstract: A method includes storing data in one of a plurality of memory slots in a queue. Each memory slot is associated with a plurality of flags. The method also includes toggling a first of the flags associated with the slot. The method further includes retrieving the data from the memory slot. In addition, the method includes toggling a second of the flags associated with the slot.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: April 25, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David J Fensore
  • Patent number: 6415343
    Abstract: A method and apparatus for dynamically assigning and enabling a unique functional address for a Universal Serial Bus device. A host assigns the unique functional address during a control transaction. The Universal Serial Bus device disables the default address and enables the unique functional address during a status stage of the control transaction to avoid an error window.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: July 2, 2002
    Assignee: National Semicondoctor Corporation
    Inventors: David J. Fensore, Kent Bruce Waterson, Gregory Lewis Dean, Robert Macomber
  • Patent number: 6353866
    Abstract: A method and apparatus for dynamically assigning and enabling a unique functional address for a Universal Serial Bus device. A host assigns the unique functional address during a control transaction. The Universal Serial Bus device disables the default address and enables the unique functional address during a status stage of the control transaction to avoid an error window.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: March 5, 2002
    Assignee: National Semiconductor Corporation
    Inventors: David J. Fensore, Kent Bruce Waterson, Gregory Lewis Dean, Robert Macomber
  • Publication number: 20020023189
    Abstract: A method and apparatus for dynamically assigning and enabling a unique functional address for a Universal Serial Bus device. A host assigns the unique functional address during a control transaction. The Universal Serial Bus device disables the default address and enables the unique functional address during a status stage of the control transaction to avoid an error window.
    Type: Application
    Filed: September 19, 2001
    Publication date: February 21, 2002
    Inventors: David J. Fensore, Kent Bruce Waterson, Gregory Lewis Dean, Robert Macomber
  • Patent number: 6205501
    Abstract: A method and apparatus for performing a control transfer on a Universal Serial Bus (USB) device. A USB device includes a memory space for reading and writing data transmitted over a USB network. The memory space is shared between a plurality of endpoints. A host initiates a control transfer by transmitting a SETUP token to a first endpoint. The endpoint must accept the SETUP token. If the first endpoint does not expect the SETUP token, or if another endpoint is active, the device stores the token until a buffer is allocated and the first endpoint is made active.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: March 20, 2001
    Assignee: National Semiconductor Corp.
    Inventors: David Brief, David J. Fensore, Kent Bruce Waterson, Gregory Lewis Dean