Abstract: A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.

Abstract: The present invention provides a method using a damascene-gate process to improve the transport properties of FETs through strain Si. Changes in mobility and FET characteristics are deliberately made in a Si or silicon-on-insulator (SOI) structure through the introduction of local strain in the channel region, without introducing strain in the device source and drain regions. The method has the advantage of not straining the source and drain regions resulting in very low leakage junctions and also it does not require any special substrate preparation like the case of a strained Si/relaxed SiGe system. Moreover, the method is compatible with existing mainstream CMOS processing. The present invention also provides a CMOS device that has a localized strained Si channel that is formed using the method of the present invention.

Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

Abstract: A semiconductor memory is described incorporating an energy conserving cyclic power source for charging and discharging the bit line with a minimum voltage across the switches. The invention overcomes the problem of power dissipation in a semiconductor memory due to charging and discharging capacitances to a voltage supply or to ground. The cyclic power supply produces a slowly varying waveform to drive the bit lines or other lines in a memory array such as a dynamic RAM in a manner so that the energy stored on those lines or in the cyclic power source is recovered at the end of the cycle.

Abstract: A toggle flip-flop circuit is described incorporating eight bi-directional switches which may be dual rail wherein each bi-directional switch for each rail includes an n and p channel transistor coupled in parallel. Clock input signals may have rise and fall times longer than the RC time constant of a bi-directional switch and node capacitance being charged which dissipates, very low power across the switch. The invention provides a practical toggle flip-flop circuit using adiabatic switching for very low power dissipation.

Abstract: An energy saving clock signal generator is disclosed including a source of multi-phase waveform signals, a shift register, and a matrix switch. The waveform source provide four, six or more waveform signals to the shift register and the matrix switch. A number of progressive pulses N.sub.pp which are an integer multiple of the number of waveform signals are applied from the shift register to the matrix switch. The matrix switch responds to the waveform signals and the progressive pulse signals to produce a number of output clock signals which may be used to drive adiabatic logic circuits.

Abstract: A combinational logic circuit composed of FETs connected together to perform a dual-rail combinatorial logic function, in which one portion of the circuitry is an original logic circuit portion that is connected to a variable power source and creates the desired logic function, and the remaining portion of the circuit is a complement logic circuit portion that is connected a constant power source and creates the complementary logic function. The two portions of the circuitry are connected together in combination at the output to form a dual-rail output signal useful for reversible computation.

Abstract: Heterojunction bipolar transistors are disclosed having an energy band offset in the valence or conduction band and the other of the bands being substantially aligned at the heterojunction. For an npn transistor the conduction band is substantially aligned and the bandgap difference is in the valence band. A pnp type transistor is also disclosed wherein all the bandgap difference is in the conduction band and the valence band is substantially aligned. The npn type transistor provides improved hole confinement in the base as well as enhanced electron injection and collection. In one embodiment of a double heterojunction bipolar transistor, materials are selected that utilize Ga compounds in the base and Al and/or In compounds in the emitter and collector, which have a valence band offset of approximately 400 meV or greater and an aligned conduction band at both of the heterojunctions.

Abstract: This invention relates generally to cryogenic amplifying-switching devices and more specifically relates to a cryogenic transistor with a superconducting base and a collector isolated from the base by a semiconductor element. Still more specifically, the invention is directed to a three terminal, transistor-like device which incorporates three metal layers. The first and second of the three layers are separated by an insulating tunnel barrier and the second and third layers are separated by a semiconductor layer of a thickness sufficient to inhibit tunnelling. The semiconductor layer has a barrier height (low) which is sufficient to permit the passage of quasiparticles from the second layer while simultaneously inhibiting the passage of Cooper pairs. The second layer is a superconductor while the first and third layers may be superconductors or normal metals. The second and third layers are connected to the semiconductor layer by means of ohmic contacts.