Abstract: An apparatus includes a sensor having an array of detectors. The sensor is configured to assign multiple detectors to a detector group corresponding to a block pixel. The sensor is also configured, for each frame of a set of frames, to apply a specified one of a set of mask patterns in order to select outputs of the detectors in the detector group and aggregate the selected outputs of the detectors in the detector group to determine pixel information for the block pixel. The apparatus also includes at least one processor configured to generate the frames using the pixel information for the block pixel, and upscale the portion of the at least one of the frames using the set of mask patterns to identify native pixels within the block pixel.

Abstract: An apparatus includes a sensor having an array of detectors. The sensor is configured to assign multiple detectors to a detector group corresponding to a block pixel. The sensor is also configured, for each frame of a set of frames, to apply a specified one of a set of mask patterns in order to select outputs of the detectors in the detector group and aggregate the selected outputs of the detectors in the detector group to determine pixel information for the block pixel. The apparatus also includes at least one processor configured to generate the frames using the pixel information for the block pixel, and upscale the portion of the at least one of the frames using the set of mask patterns to identify native pixels within the block pixel.

Abstract: A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.

Abstract: Methods and apparatus for a sensing system having a focal plane array having an n×m array of sensing elements and a single output pixel and a mask to select or deselect ones of the sensing elements in the array to form patterns, wherein the mask forms a part of the focal plane array.

Abstract: Methods and apparatus for a sensing system having a focal plane array having an n×m array of sensing elements and a single output pixel and a mask to select or deselect ones of the sensing elements in the array to form patterns, wherein the mask forms a part of the focal plane array.

Abstract: An arrangement for making electrical contact to a vertical capacitor having top and bottom metal layers separated by a dielectric, and at least one trench. Recesses are formed in an oxide layer over the capacitor to provide access to the top and bottom metal layers. The recesses include contacting portions preferably positioned such that there is no overlap between them and any of the trenches. Metal in the recesses, preferably copper, forms electrical contacts to the vertical capacitor's metal layers and enables reliable bonding to copper metallization on other layers such as an ROIC layer. ‘Dummy’ capacitors may be tiled on portions of the IC where there are no vertical capacitors, preferably with the top surfaces of their top metal at a height approximately equal to that of the top surface of the vertical capacitor's top metal, thereby enabling the IC to be planarized with a uniform planarization thickness.

Abstract: An infrared detector system is provided for detecting infrared radiation from an infrared radiation source or a scene. The system includes a first area that is semiconductor-based and biased to produce negative luminescence, the first area including at least one semiconductor-based detector. The detector system further includes at least one additional area being semiconductor-based and biased to produce negative luminescence. A low-emissivity specular retro-reflector shield is configured to reflect infrared radiation and covers the first area and the at least one additional area. The shield defines an aperture to allow the at least one semiconductor-based detector to receive incident rays of the infrared radiation from the infrared radiation source or the scene via a low-scatter, low-emission optical system such that the radiation incident from the infrared radiation source or scene substantially fills the solid angle defined by the aperture at any point in the first area.

Abstract: An arrangement for making electrical contact to a vertical capacitor having top and bottom metal layers separated by a dielectric, and at least one trench. Recesses are formed in an oxide layer over the capacitor to provide access to the top and bottom metal layers. The recesses include contacting portions preferably positioned such that there is no overlap between them and any of the trenches. Metal in the recesses, preferably copper, forms electrical contacts to the vertical capacitor's metal layers and enables reliable bonding to copper metallization on other layers such as an ROIC layer. ‘Dummy’ capacitors may be tiled on portions of the IC where there are no vertical capacitors, preferably with the top surfaces of their top metal at a height approximately equal to that of the top surface of the vertical capacitor's top metal, thereby enabling the IC to be planarized with a uniform planarization thickness.

Abstract: An infrared detector system is provided for detecting infrared radiation from an infrared radiation source or a scene. The system includes a first area that is semiconductor-based and biased to produce negative luminescence, the first area including at least one semiconductor-based detector. The detector system further includes at least one additional area being semiconductor-based and biased to produce negative luminescence. A low-emissivity specular retro-reflector shield is configured to reflect infrared radiation and covers the first area and the at least one additional area. The shield defines an aperture to allow the at least one semiconductor-based detector to receive incident rays of the infrared radiation from the infrared radiation source or the scene via a low-scatter, low-emission optical system such that the radiation incident from the infrared radiation source or scene substantially fills the solid angle defined by the aperture at any point in the first area.

Abstract: A capacitive trans-impedance amplifier circuit with charge injection compensation is provided. A feedback capacitor is connected between an inverting input port and an output port of an amplifier. A MOS reset switch has source and drain terminals connected between the inverting input and output ports of the amplifier, and a gate terminal controlled by a reset signal. The reset switch is open or inactive during an integration phase, and closed or active to electrically connect the inverting input port and output port of the amplifier during a reset phase. One or more compensation capacitors are provided that are not implemented as gate oxide or MOS capacitors. Each compensation capacitor has a first port connected to a compensation signal that is a static signal or a toggling compensation signal that toggles between two compensation voltage values, and a second port connected to the inverting input port of the amplifier.

Abstract: A capacitive trans-impedance amplifier circuit with charge injection compensation is provided. A feedback capacitor is connected between an inverting input port and an output port of an amplifier. A MOS reset switch has source and drain terminals connected between the inverting input and output ports of the amplifier, and a gate terminal controlled by a reset signal. The reset switch is open or inactive during an integration phase, and closed or active to electrically connect the inverting input port and output port of the amplifier during a reset phase. One or more compensation capacitors are provided that are not implemented as gate oxide or MOS capacitors. Each compensation capacitor has a first port connected to a compensation signal that is a static signal or a toggling compensation signal that toggles between two compensation voltage values, and a second port connected to the inverting input port of the amplifier.

Abstract: An imaging array comprises a photodetector layer, a readout IC (ROIC) layer, and a charge storage capacitor layer which is distinct from the photodetector and ROIC layers; the layers are electrically interconnected to form the array. The capacitors within the charge storage capacitor layer are preferably micromachined; the charge storage capacitor layer can be an interposer layer or an outer layer.

Abstract: An imaging array comprises a photodetector layer, a readout IC (ROIC) layer, and a charge storage capacitor layer which is distinct from the photodetector and ROIC layers; the layers are electrically interconnected to form the array. The capacitors within the charge storage capacitor layer are preferably micromachined; the charge storage capacitor layer can be an interposer layer or an outer layer.

Abstract: A unit cell (20) is disclosed that has an input node for coupling to an output of a detector (D1) of electromagnetic radiation, such as IR or visible radiation. The unit cell includes a first capacitor (CintA) switchably coupled to the input node for receiving a charge signal from the detector, and for integrating the charge signal during a first integration period, as well as a second capacitor (CintB)switchably coupled to the input node for integrating the charge signal during a second integration period. The unit cell further includes an output multiplexer (32, 34) for selectively coupling the first capacitor and the second capacitor to an output signal line (38) during respective charge signal readout periods. In the preferred embodiment a duration of the first integration period is one of greater than or less than the second integration period, and the first integration period is one of non-overlapping or overlapping with the second integration period, and vice versa.

Abstract: Disclosed is a High Dynamic Range Dual Mode (HDR-DM) input circuit unit cell (10) for use with an infrared (IR) radiation detector (D1). The readout circuit unit cell includes a plurality of transistors (M1, M2, M3 and M4), switches (S1, S2 and S3), and capacitances (Cfb, Cbl and CSH) that are controllably coupled together to form, in a first mode of operation below an illumination level threshold, a CTIA input circuit (12), and to form, in a second mode of operation above the illumination level threshold, a lower gain SFD input circuit (14).

Abstract: A unit cell (20) is disclosed that has an input node for coupling to an output of a detector (D1) of electromagnetic radiation, such as IR or visible radiation. The unit cell includes a first capacitor (CintA) switchably coupled to the input node for receiving a charge signal from the detector, and for integrating the charge signal during a first integration period, as well as a second capacitor (CintB)switchably coupled to the input node for integrating the charge signal during a second integration period. The unit cell further includes an output multiplexer (32, 34) for selectively coupling the first capacitor and the second capacitor to an output signal line (38) during respective charge signal readout periods. In the preferred embodiment a duration of the first integration period is one of greater than or less than the second integration period, and the first integration period is one of non-overlapping or overlapping with the second integration period, and vice versa.

Abstract: In a first aspect of these teachings there is provided a radiation sensor that includes sensor optics having an entrance aperture and a two dimensional array of unit cells (10) spaced away from the aperture. Each unit cell includes a radiation detector (D1) having an output coupled to an input of a gain element, and each gain element is constructed so as to have at least one component with a value selected to set the gain of the gain element to a value that is a function of the unit cell's location along an x-axis and along a y-axis within the two dimensional array. In this manner a compensation is made for a variation of scene illumination across the two dimensional array, where the variation in scene illumination results from a relative intensity of the energy impinging on a unit area of the two dimensional array that varies, for example, by the fourth power of cosine &thgr;, where &thgr; is an angle referenced to an optical axis of the radiation sensor.