Abstract: First data is stored. A request for the first data is received from a communication device over a link established with a communication device. An access control engine comprising circuitry is to control access to the first data to the communication device based on an authentication state of the communication device and a protection state of the link.

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

Abstract: A system comprising a discrete graphics system-on-chip (SoC) to couple to a host processor unit, the SoC comprising a memory bridge comprising a first port to receive requests sent by a compute engine through a first path to the memory; and a second port to receive requests sent by a plurality of agents of the SoC through a second path to the memory.

Abstract: An apparatus comprises a first tile comprising a first instance of a plurality of global endpoints and a first instance of a plurality of local networks comprising a plurality of local endpoints; and an interconnect network of the first tile to couple to an interconnect network of a second tile, the second tile comprising a second instance of the plurality of global endpoints and a second instance of the plurality of local networks comprising the plurality of local endpoints; wherein the interconnect network utilizes an address space comprising unique identifiers for the plurality of global endpoints of the first and second tiles; and non-unique identifiers for the plurality of local endpoints of the first and second tiles, wherein non-unique identifiers are reused in multiple local networks of the plurality of local networks of the first and second tiles.

Abstract: A system comprising a discrete graphics system-on-chip (SoC) to couple to a host processor unit, the SoC comprising a fabric comprising a handler circuitry to decode a request from a compute engine, the handler circuitry to route the request based on an opcode included in the request, the handler configured to decode the opcode from a set of opcodes for use in requests by the compute engine, wherein the set of opcodes include opcodes corresponding to a first write request type and a first read request type, wherein requests of the first write request type and the first read request type are routed to either the host memory or the graphics memory; and a second write request type and a second read request type, wherein requests of the second write request type and the second request type are to be routed to the sideband network.

Abstract: In one embodiment, a device includes: an interface circuit to couple the device to a host via a link, where in a first mode the interface circuit is to be configured as an integrated switch controller and in a second mode the interface circuit is to be configured as a link controller; and a fabric coupled to the interface circuit, the fabric to couple to a plurality of hardware circuits, where the fabric is to be dynamically configured for one of the first mode or the second mode based on link training of the link. Other embodiments are described and claimed.

Abstract: A port of a computing device includes protocol circuitry to implement a particular interconnect protocol, where the protocol circuitry is to generate a set of ordered sets defined according to the particular interconnect protocol. The set of ordered sets is generated for a link to couple a first device to a second device and the set of ordered sets comprises link information for the link. Translation layer circuitry is provided to: generate, from the set of ordered sets, at least one data structure to comprise at least a portion of the link information, and cause the data structure to be sent from the first device to the second device on the link in lieu of the set of ordered sets.

Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.

Abstract: A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.

Abstract: Aspects of the disclosure are directed to systems, methods, and devices that include an application processor. The application processor includes an interface logic to interface with a communication module using a bidirectional interconnect link compliant with a peripheral component interconnect express (PCIe) protocol. The interface logic to receive a data packet from across the link, the data packet comprises a header and data payload; determine a hint bit set in the header of the data packet; determine a steering tag value in the data packet header based on the hint bit set; and transmit the data payload to non-volatile memory based on the steering tag set in the header.

Abstract: A protected link between a first computing device and a second computing device is set up, wherein communication over the protected link is to comply with a communication protocol that allows packets to be reordered during transit. A plurality of packets are generated according to a packet format that ensures the plurality of packets will not be reordered during transmission over the protected link, the plurality of packets comprising a first packet and a second packet. Data of the plurality of packets are encrypted for transmission over the protected link, wherein data of the first packet is encrypted based on the cryptographic key and a first value of a counter and data of the second packet is encrypted based on the cryptographic key and a second value of the counter.

Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.

Abstract: Embodiments described herein may be directed to apparatus, systems, techniques, or processes for a routing mechanism based on the Stream ID field, already present in IDE TLPs, applicable to switches, root complexes (RC) and multifunction devices. This in turn allows additional header content for IDE TLPs to be encrypted instead of being sent in the clear (not encrypted). Additionally, Stream routing may be used for non-IDE TLPs as well by allowing the inclusion and application of the Stream mechanism to non-IDE TLPs. Other embodiments may be described and/or claimed.

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

Abstract: A protected link between a first computing device and a second computing device is set up, wherein communication over the protected link is to comply with a communication protocol that allows packets to be reordered during transit. A plurality of packets are generated according to a packet format that ensures the plurality of packets will not be reordered during transmission over the protected link, the plurality of packets comprising a first packet and a second packet. Data of the plurality of packets are encrypted for transmission over the protected link, wherein data of the first packet is encrypted based on the cryptographic key and a first value of a counter and data of the second packet is encrypted based on the cryptographic key and a second value of the counter.

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.