Abstract: An anti-resonance system for a blade defining an elongated channel therein and affixed to a helicopter rotor includes a moveable mass disposed within the elongated channel of the blade so as to be able to slide along elongated channel. A moving device coupled to the moveable mass is configured to move the moveable mass within the elongated channel. A controller is configured to cause the moving device to move the moveable mass to a selected position within the elongated channel so as to avoid the additional resonance vibrations of the blade during a rotor speed change. In a method of avoiding resonance of a helicopter blade, a current rotational speed of the blade is determined. A position of the movable mass so as to avoid a resonance point at a current rotational speed is obtained. The moveable mass is moved to the position.

Abstract: Pyrrolidine main protease inhibitors are described that are effective as antiviral compounds.

Abstract: A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control.

Abstract: A method and apparatus for use in read/write operations by a processor that reads and writes information in first and second address formats. The method and apparatus include a memory and a memory mapper for remapping according to a predetermined scheme those memory fragments not containing information stored in the first address format. Memory fragments are thus accessible to the processor for reading and writing information in the second address format. Such remapping operation results in the memory fragments appearing logically contiguous. In the preferred embodiment, the first address format is an x-y address format and the second address format is a linearly addressable format. An alternative embodiment discloses the use of a second memory for reading and writing information in the second address format. In that embodiment, the memory mapper remaps the memory fragments to appear logically contiguous with said second memory.