Abstract: An electronic computing device including at least one processing unit that implements a specific fault signal upon experiencing an associated fault, a control unit that generates a specific recovery signal upon receiving the fault signal from the at least one processing unit, and at least one input memory unit. The recovery signal initiates specific recovery processes in the at least one processing unit. The input memory buffers input data signals input to the at least one processing unit that experienced the fault during the recovery period.

Abstract: Combining signals includes receiving first signals having a first frequency and second signals having a second frequency. A first weight reflecting a signal-to-noise ratio associated with a first signal is determined for each first signal, and a first signal output is generate from the first signals in accordance with the first weights. A second weight reflecting a signal-to-noise ratio associated with a second signal is determined for each second signal, and a second signal output is generate from the second signals in accordance with the second weights. The first signal output and the second signal output are combined to yield a combined signal output.

Abstract: An electronic computing device including at least one processing unit that implements a specific fault signal upon experiencing an associated fault, a control unit that generates a specific recovery signal upon receiving the fault signal from the at least one processing unit, and at least one input memory unit. The recovery signal initiates specific recovery processes in the at least one processing unit. The input memory buffers input data signals input to the at least one processing unit that experienced the fault during the recovery period.

Abstract: Combining signals includes receiving first signals having a first frequency and second signals having a second frequency. A first weight reflecting a signal-to-noise ratio associated with a first signal is determined for each first signal, and a first signal output is generate from the first signals in accordance with the first weights. A second weight reflecting a signal-to-noise ratio associated with a second signal is determined for each second signal, and a second signal output is generate from the second signals in accordance with the second weights. The first signal output and the second signal output are combined to yield a combined signal output.

Abstract: Combining signals includes receiving first signals having a first frequency and second signals having a second frequency. A first weight reflecting a signal-to-noise ratio associated with a first signal is determined for each first signal, and a first signal output is generate from the first signals in accordance with the first weights. A second weight reflecting a signal-to-noise ratio associated with a second signal is determined for each second signal, and a second signal output is generate from the second signals in accordance with the second weights. The first signal output and the second signal output are combined to yield a combined signal output.

Abstract: Combining signals includes receiving first signals having a first frequency and second signals having a second frequency. A first weight reflecting a signal-to-noise ratio associated with a first signal is determined for each first signal, and a first signal output is generate from the first signals in accordance with the first weights. A second weight reflecting a signal-to-noise ratio associated with a second signal is determined for each second signal, and a second signal output is generate from the second signals in accordance with the second weights. The first signal output and the second signal output are combined to yield a combined signal output.

Abstract: A perfect integrator emulator includes a first multiplier multiplying an input with a first constant, KNEW, and generating a scaled input, a summer summing the scaled input with a previously generated scaled output and generating an accumulated output, a delay adding a predetermined amount of delay to the accumulated output and generating a delayed output, a second multiplier multiplying the delayed output with a second constant, KOLD, and generating the scaled output. The constants KNEW and KOLD are chosen such that the accumulated output emulates a perfect integrator's relative weighting, and saturation protection is guaranteed.

Abstract: A perfect integrator emulator includes a first multiplier multiplying an input with a first constant, KNEW, and generating a scaled input, a summer summing the scaled input with a previously generated scaled output and generating an accumulated output, a delay adding a predetermined amount of delay to the accumulated output and generating a delayed output, a second multiplier multiplying the delayed output with a second constant, KOLD, and generating the scaled output. The constants KNEW and KOLD are chosen such that the accumulated output emulates a perfect integrator's relative weighting, and saturation protection is guaranteed.

Abstract: A perfect integrator emulator includes a first multiplier multiplying an input with a first constant, KNEW, and generating a scaled input, a summer summing the scaled input with a previously generated scaled output and generating an accumulated output, a delay adding a predetermined amount of delay to the accumulated output and generating a delayed output, a second multiplier multiplying the delayed output with a second constant, KOLD, and generating the scaled output. The constants KNEW and KOLD are chosen such that the accumulated output emulates a perfect integrator's relative weighting, and saturation protection is guaranteed.