Patents by Inventor David J. Riddoch
David J. Riddoch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11876880Abstract: A data processing system is provided. A host processing device supports a host transport engine operable to establish a first transport stream over a network with a remote peer. Device hardware comprises a device transport engine. The device transport engine is configured to monitor the first transport stream to determine a state of the first transport stream and in response to an indication from the host processing device perform transport processing of the first transport stream.Type: GrantFiled: October 6, 2016Date of Patent: January 16, 2024Assignee: Xilinx, Inc.Inventors: Steve L. Pope, David J. Riddoch
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Patent number: 11847108Abstract: A system has data capture devices collecting data from different points in a network. The captured data is written to a data store and is directed to an output. The data from the different data capture devices can be delivered to a data analytics device. As long as the data analytics device is able to keep pace with the data that is directed to the output, that data is used by the analytics device. If the analytics device is not able to keep pace, the data written to the data store is retrieved and is used until the analytics device has caught up.Type: GrantFiled: October 8, 2019Date of Patent: December 19, 2023Assignee: XILINX, INC.Inventors: Steven L. Pope, David J. Riddoch, Matthew Knight
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Patent number: 11809367Abstract: A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured to store an indication that at least some of the data for transmission has been transferred to the buffer wherein the indication is associated with a descriptor pointing to the buffer.Type: GrantFiled: May 5, 2021Date of Patent: November 7, 2023Assignee: Xilinx, Inc.Inventors: Steven L. Pope, David J. Riddoch, Dmitri Kitariev
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Patent number: 11695669Abstract: A network interface device, said network interface device has a data transmission path configured to receive data for transmission. The data for transmission is to be sent over a network by the network interface device. A monitor is configured to monitor the data transmission path to determine if an underrun condition is associated with the data transmission path. If so, an indication is included in the transmitted data packet.Type: GrantFiled: May 24, 2021Date of Patent: July 4, 2023Assignee: Xilinx, Inc.Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
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Patent number: 11693777Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.Type: GrantFiled: October 4, 2021Date of Patent: July 4, 2023Assignee: Xilinx, Inc.Inventors: Steven L. Pope, Dmitri Kitariev, David J. Riddoch, Derek Roberts, Neil Turton
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Publication number: 20230006945Abstract: Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry.Type: ApplicationFiled: July 18, 2022Publication date: January 5, 2023Applicant: Xilinx, Inc.Inventors: Steven L. Pope, Derek Roberts, David J. Riddoch, Dmitri Kitariev
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Publication number: 20220400147Abstract: A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.Type: ApplicationFiled: July 18, 2022Publication date: December 15, 2022Applicant: Xilinx, Inc.Inventors: Steven L. Pope, Derek Roberts, David J. Riddoch
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Patent number: 11502845Abstract: A network interface device comprises an integrated circuit device comprises at least one processor. A network interface device comprises a memory. The integrated device is configured to execute a function with respect to at least a part of stored data in said memory.Type: GrantFiled: July 6, 2020Date of Patent: November 15, 2022Assignee: Xilinx, Inc.Inventors: Steven L. Pope, David J. Riddoch, Paul Fox
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Patent number: 11489876Abstract: A rule engine receives data flows. The data flows are between a network and an application. The rule engine determines data flow information and in dependence on the information performs an action with respect to said flow. A controller provides control information to the rule engine to define one or more actions. The communications between said rule engine and said controller are secure.Type: GrantFiled: March 11, 2020Date of Patent: November 1, 2022Assignee: Xilinx, Inc.Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
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Patent number: 11425231Abstract: Data is received at a buffer used by a protocol processing stack which protocol processes the received data. The received data is made available to, for example, an application, before the protocol processing of the data is complete. If the protocol processing is successful, the data made available to the application is committed.Type: GrantFiled: September 29, 2020Date of Patent: August 23, 2022Assignee: Xilinx, Inc.Inventors: Steve Pope, Kieran Mansley, Sian James, David J. Riddoch
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Patent number: 11409569Abstract: A data processing system being configured to select between different hardware resources for the running of an application configured for the sending and receiving of data over a network. The selection of hardware resources may be between resources on the network interface device, and hardware resources on the host. The selection of hardware resources may be between first and second hardware resources on the network interface device. An API is provided in the data processing system that responds to requests from the application irrespective of the hardware on which the application is executing.Type: GrantFiled: March 29, 2018Date of Patent: August 9, 2022Assignee: XILINX, INC.Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
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Patent number: 11392429Abstract: A data processing system comprising: an operating system providing an application programming interface; an application supported by the operating system and operable to make calls to the application programming interface; an intercept library configured to intercept calls of a predetermined set of call types made by the application to the application programming interface; and a configuration data structure defining at least one action to be performed for each of a plurality of sequences of one or more calls having predefined characteristics, the one or more calls being of the predetermined set of call types; wherein the intercept library is configured to, on intercepting a sequence of one or more calls defined in the configuration data structure, perform the corresponding action(s) defined by the configuration data structure.Type: GrantFiled: January 15, 2019Date of Patent: July 19, 2022Assignee: XILINX, INC.Inventors: Steven L. Pope, David J. Riddoch, Kieran Mansley
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Patent number: 11394664Abstract: Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry.Type: GrantFiled: May 8, 2020Date of Patent: July 19, 2022Assignee: Xilinx, Inc.Inventors: Steven L. Pope, Derek Roberts, David J. Riddoch, Dmitri Kitariev
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Patent number: 11394768Abstract: A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.Type: GrantFiled: May 14, 2020Date of Patent: July 19, 2022Assignee: Xilinx, Inc.Inventors: Steven L. Pope, Derek Roberts, David J. Riddoch
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Patent number: 11374777Abstract: A data processing system comprising: a processing subsystem supporting a plurality of consumers, each consumer being arranged to process messages received into a corresponding receive queue; a network interface device supporting a virtual interface for each of the receive queues; and a hardware accelerator coupled to the processing subsystem by the network interface device and configured to parse one or more streams of data packets received from a network so as to, for each consumer: identify in the data packets messages having one or more of a set of characteristics associated with the consumer; and frame the identified messages in a new stream of data packets addressed to a network endpoint associated with the virtual interface of the consumer so as to cause said new stream of data packets to be delivered into the receive queue of the consumer.Type: GrantFiled: November 25, 2019Date of Patent: June 28, 2022Assignee: XILINX, INC.Inventors: Steve L. Pope, David J. Riddoch
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Patent number: 11249938Abstract: A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured to store an indication that at least some of the data for transmission has been transferred to the buffer wherein the indication is associated with a descriptor pointing to the buffer.Type: GrantFiled: August 26, 2019Date of Patent: February 15, 2022Assignee: XILINX, INC.Inventors: Steven L. Pope, David J. Riddoch, Dmitri Kitariev
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Publication number: 20220027273Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.Type: ApplicationFiled: October 4, 2021Publication date: January 27, 2022Applicant: Xilinx, Inc.Inventors: Steven L. Pope, Dmitri Kitariev, David J. Riddoch, Derek Roberts, Neil Turton
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Patent number: 11165683Abstract: A network interface device, said network interface device has a data transmission path configured to receive data for transmission. The data for transmission is to be sent over a network by the network interface device. A monitor is configured to monitor the data transmission path to determine if an underrun condition is associated with the data transmission path. If so, an indication is included in the transmitted data packet.Type: GrantFiled: December 20, 2016Date of Patent: November 2, 2021Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
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Patent number: 11138116Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.Type: GrantFiled: July 29, 2019Date of Patent: October 5, 2021Assignee: XILINX, INC.Inventors: Steven L. Pope, Dmitri Kitariev, David J. Riddoch, Derek Roberts, Neil Turton
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Patent number: 11134140Abstract: A data processing system is provided. A host processing device supports a host transport engine operable to establish a first transport stream over a network with a remote peer. Device hardware comprises a device transport engine. The device transport engine is configured to monitor the first transport stream to determine a state of the first transport stream and in response to an indication from the host processing device perform transport processing of the first transport stream.Type: GrantFiled: April 6, 2017Date of Patent: September 28, 2021Assignee: Xilinx, Inc.Inventors: Steve L. Pope, David J. Riddoch