Abstract: A mechanism is provided for automatically performing join operations. Source data is received and a metadata model is received. The metadata model includes a hierarchical structure. The source data is aligned to the hierarchical structure in the metadata model to form a source data hierarchy. Based on the source data hierarchy, the source data is joined to geocoded information.

Abstract: In certain examples, a mechanism is provided for automatically performing join operations. Source data is received and a metadata model is received. The metadata model includes a hierarchical structure. The source data is aligned to the hierarchical structure in the metadata model to form a source data hierarchy. Based on the source data hierarchy, the source data is joined to geocoded information.

Abstract: A multi-channel data transfer circuit and method which provides an interface between a computer system and a multi-channel communication controller. The data transfer circuit is programmable to provide a selectable number of communication channels between the computer system and the communication controller. The data transfer circuit is further programmable to provide a selectable number of entries in each of the communication channels. In a particular embodiment, FIFO memories within the data transfer circuit are logically partitioned to provide the desired number of communication channels and the desired number of entries per channel. The data transfer circuit includes a multi-channel transmit circuit for providing data values from the computer system to the communication controller, and a multi-channel receive circuit for providing data values from the computer communication controller to the computer system.

Abstract: An on-chip bus structure for use in a modularized integrated circuit chip including an FPGA module(s). The bus is intended for memory mapped data transfers between circuit modules, for instance master, slave, master/slave, bus controller, and bus monitor type modules. Each circuit module is an on-chip function block including a bus interface and communicates by a predefined set of bus signals; at least one module is an FPGA (field programmable gate array). Each module acts as a bus master when it initiates data read or write operations, or may be addressed during a bus read/write operation and thereby acts as a bus slave. This bus and module structure allows implementation of a system on a single chip.

Abstract: In a programmable logic device having I/O blocks and logic blocks, two lines leading from a region including a logic block and an I/O block alternately provide a logic block output signal and its complement or a logic block output signal and an I/O block input signal. A multiplexer selects between providing on a line leading from an I/O block to an interconnect structure a first signal which is provided by the I/O block when the I/O block is an input buffer and a second signal which is the inverse of a logic signal provided to the I/O block when the I/O block is not an input buffer. Thus in one case two lines which extend from the I/O block to the interconnect structure may carrya) a logic block output signal andb) an I/O block output signal;and in the other case carrya) a logic block output signal andb) the inverse of the logic block output signal.