Abstract: A process includes emulating, by a programmable logic device, a hardware component to provide an emulated hardware component. The emulated hardware component is capable of exercising the predetermined functionality. The process includes testing the emulated hardware component. The process includes determining, by the programmable logic device, whether the emulated hardware component exercised the predetermined functionality during the test. The determination includes, responsive to the testing, detecting, by a state sequence detector of the programmable logic device, whether the emulated hardware component sequenced through a plurality of states associated with the predetermined functionality. The process includes, responsive to the detection of whether the emulated hardware component sequenced through the plurality of states, generating, by the programmable logic device, an indicator representing a coverage of the predetermined functionality by the testing.

Abstract: A joint assembly for joining a first component to a second component, including a first clevis including first clevis apertures and a second clevis including second clevis apertures, first bearing insert and a second bearing insert fixedly coupled to the first clevis and the second clevis, respectively, a ring surrounding the first clevis and the second clevis and including a plurality of ring apertures, a plurality of pins received within the corresponding ring aperture, where pin includes a head portion and a shaft portion extending from the head portion, where the shaft portion is coupled to the ring by a corresponding interference fit, where further the shaft portion is coupled to the corresponding first or second bearing inserts by a corresponding clearance fit such that the shaft portion is rotatable relative to the corresponding first or second bearing inserts.

Abstract: Relocation and/or replacement of terminal apparatus in telecommunications systems including, but not necessarily limited to, key telephone systems, usually entails reassignment of administration data; for example, features. When a station or terminal apparatus is moved physically from one port to another within a telecommunications system which comprises a plurality of ports connected to a central processor, interface means operative on initial connection of said terminal apparatus transmits to the central processor an identifier unique to such terminal apparatus within such system. The central processing means has storage for each said identifier together with administration data specific to said terminal apparatus and the number of the port to which said terminal apparatus set is connected. Following receipt of an identifier, the central processor updates said storage means to assign said administration data corresponding to said identifier to the present port.

Abstract: A key telephone system includes a plurality of ports being linked by port associated bidirectional communication channels which are synchronously switched by transferring bit states between ones of the channels to provide communication paths between the ports as directed by a central processor. The ports are also linkable to and via the central processor by port associated message channels. An interface circuit is responsive to the central processor and message channel signals for regulating flow of messages received by the central processor and for effecting single and plural channel distribution of messages from the central processor. The message channels permit telephony operating features and functions to be provided either within the central processor or by appropriate apparatus means being connected at any of the ports.

Abstract: Communication paths in a digital key telephone system are operated by sequentially transferring bit states from origin channels associated with communication ports to exclusively dedicated time slots in a parallel transmission medium. Time slot bit states are selectively stored at designated memory locations corresponding to destination channels associated with the communication ports. The memory locations are read in synchronism with the channel occurrences and bit states from the designated memory locations are asserted in the corresponding channels, any remaining channels having predetermined bit states asserted therein.

Abstract: A digital tape timer containing a counter and associated arithmetic control and timing logic to detect the relative tape position and provide a time-multiplexed, binary coded decimal (BCD) output for the display of the tape position in hours, minutes, seconds and/or tenths of seconds of play/record time at any of the selected tape speeds. The timer employs an eight digit format; five digits are displayed and one of the three remaining digits becomes the least significant digit whose modulus is altered to present the correct division rate to the incoming tach pulses. The counter generates serial digits with one digit appearing on a selected line, whereby all eight digits are transmitted using four wires for the binary code plus one wire for selection of each digit to be displayed. Thus, the system inherently provides the added advantage of time-multiplexing of the timer system output.