Patents by Inventor David J. Stanek

David J. Stanek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9001450
    Abstract: A method of correcting repeatable run out (RRO) errors for a HDD in which RRO data is instead stored in consolidated form within the reserved area of the disk, instead of storing RRO data in the servo patterns for each HDD track or sector. RRO data is preferably stored in the reserved area of a hard disk drive in compressed form. The compressed RRO data is subsequently read into DRAM in compressed form and then decompressed for use. Predictive techniques determine what compressed RRO data is needed for upcoming read/write operations.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 7, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Jonathan D. Coker, Jeffrey L. Furlong, David R. Hall, David J. Stanek
  • Publication number: 20130342929
    Abstract: A method of correcting repeatable run out (RRO) errors for a HDD in which RRO data is instead stored in consolidated form within the reserved area of the disk, instead of storing RRO data in the servo patterns for each HDD track or sector. RRO data is preferably stored in the reserved area of a hard disk drive in compressed form. The compressed RRO data is subsequently read into DRAM in compressed form and then decompressed for use. Predictive techniques determine what compressed RRO data is needed for upcoming read/write operations.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 26, 2013
    Applicant: HGST NETHERLANDS B.V.
    Inventors: Jonathan D. Coker, Jeffrey L. Furlong, David R. Hall, David J. Stanek
  • Patent number: 7193802
    Abstract: An apparatus for providing dynamic equalizer optimization is disclosed. The present invention solves the above-described problems by providing equalizer coefficient updates that converge towards the same solution as the direct method without having to first write a known pattern to the disk or requiring any prior knowledge of the data already written on the disk. The adaptive cosine function may be used to modify only a DFIR tap set, only the j and k parameters of a cosine equalizer or to modify both the tap set for a DFIR filter and the j and k parameters of the cosine equalizer. Another algorithm, such as the LMS algorithm, may be used to modify parameters not modified by the cosine algorithm.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: March 20, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos S. Eleftheriou, Richard L. Galbraith, Weldon M. Hanson, Thomas Mittelholzer, Travis R. Oenning, Michael J. Ross, David J. Stanek
  • Patent number: 6812867
    Abstract: Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: November 2, 2004
    Assignee: International Business Machines Corp.
    Inventors: Roy D Cideciyan, Ajay Dholakia, Evangelos S Eleftheriou, Richard L Galbraith, Thomas Mittelholzer, Travis R Oenning, David J Stanek
  • Publication number: 20030227397
    Abstract: Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream.
    Type: Application
    Filed: June 5, 2003
    Publication date: December 11, 2003
    Applicant: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos S. Eleftheriou, Richard L. Galbraith, Thomas Mittelholzer, Travis R. Oenning, David J. Stanek
  • Publication number: 20020178422
    Abstract: A method and apparatus for maximum likelihood detection of a sequential stream of binary bits. 2N binary states (N≧2) are projected onto a trellis at a sequence of times. Two branches to each binary state at time Ti+1 from a closest previous time Ti are identified (i≧N). There are 2N+1 such branches between Ti and Ti+1. A state metric for each of the 2N binary states at Ti and a branch metric for each of the 2N+1 branches between Ti and Ti+1 are provided. An illegal branch and a legal branch to a state S1 at time Ti+1 are so designated. A state metric is computed at each of the 2N binary states at time Ti+1 as a function of: the state metrics at Ti, the branch metrics between Ti and Ti+1, and the 2 branches to state S1.
    Type: Application
    Filed: April 11, 2001
    Publication date: November 28, 2002
    Applicant: International Business Machines Corporation
    Inventors: Richard L. Galbraith, Allen P. Haar, David J. Stanek
  • Patent number: 6158027
    Abstract: A noise-predictive data detection method and apparatus are provided for enhanced noise-predictive maximum-likelihood (NPML) data detection in a direct access storage device. A data signal from a data channel in the direct access storage device is applied to a maximum-likelihood detector that provides an estimated sequence signal. A noise bleacher filter having a frequency response of (1+.alpha.D)/1-.beta.D.sup.2) receives a combined estimated sequence signal and data signal and provides a noise filtered signal. A matching and error event filter receives the noise filtered signal and provides an error event filtered signal. An error correction unit receives the estimated sequence signal from the maximum-likelihood detector and receives the error event filtered signal and provides an error corrected estimated sequence signal.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: December 5, 2000
    Assignee: International Business Machines Corporation
    Inventors: Gregory S. Bush, Roy D. Cideciyan, Jonathan D. Coker, Evangelos S. Eleftheriou, Richard L. Galbraith, David J. Stanek
  • Patent number: 5426541
    Abstract: Apparatus and method for providing equalization adjustment for a filter are provided in a PRML data channel. A first predetermined test pattern is written. Relative error is measured in both magnitude and phase for predetermined frequencies. A relative magnitude ratio for the predetermined frequencies and a phase delay between the predetermined frequencies are identified. A tap set is generated having predefined frequency responses at a plurality of predefined discrete frequencies.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: June 20, 1995
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Coker, Richard L. Galbraith, Walter Hirt, David J. Stanek, Mark D. Warne