Abstract: A method and apparatus are provided for implementing soft-input soft-output iterative detectors/decoders. Soft-input information is added directly to incoming channel samples. Input signals comprising the received incoming channel samples with the added soft-input information are detected using a detector trellis. Branch metric terms are transformed to shift all time varying terms with the added soft-input information and some constant terms after an add compare select (ACS) unit. The shifted time varying terms with the added soft-input information and the shifted constant terms are added directly to state metric terms. The soft-input information is added directly to incoming channel samples and the computation of branch metrics is not affected. This allows optimization of a dual-max detector and soft-input soft-output Viterbi detector architectures to minimize hardware complexity and power consumption.

Abstract: Methods and apparatus for enhanced timing loop are provided for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). An acquisition timing circuit for generating an acquisition timing signal includes a plurality of compare functions for receiving and comparing consecutive input signal samples on an interleave with a threshold value. The acquisition timing circuit includes a majority rule voting function coupled to the plurality of compare functions for selecting a timing interleave. Tracking timing circuitry for generating a timing error signal during a read operation includes a channel data detector. The channel data detector receives disk signal input samples and includes a multiple-state path memory. The tracking timing circuit includes a low latency detector receiving disk signal input samples. A selector function is coupled to an output of the low latency detector and is coupled to the multiple-state path memory for selecting a state.

Abstract: An apparatus and method for transferring data between a read/write transducer coupled to a data channel and a data storage medium eliminates the necessity of a data sector block coding pad field. A data sector is received during a read operation. A disable signal associated with a last block of the data sector is generated. In response to the disable signal, data correction, such as parity correction, to the last block of the data sector is disabled. Data correction is enabled for application to blocks of the data sector other than the last block. Generating the disable signal involves identifying the last block of the data sector, which may be accomplished by detecting a change of state of a read gate input into the data channel or by use of a counter. The apparatus and method of the present invention may be embodied within a data channel of a data storing system, such as a direct access storage system.

Abstract: An apparatus and method for transferring data between a read/write transducer coupled to a data channel and a data storage medium eliminates the necessity of a data sector block coding pad field. A data sector is received during a read operation. A disable signal associated with a last block of the data sector is generated. In response to the disable signal, data correction, such as parity correction, to the last block of the data sector is disabled. Data correction is enabled for application to blocks of the data sector other than the last block. Generating the disable signal involves identifying the last block of the data sector, which may be accomplished by detecting a change of state of a read gate input into the data channel or by use of a counter. The apparatus and method of the present invention may be embodied within a data channel of a data storing system, such as a direct access storage system.

Abstract: A method and apparatus are provided for implementing soft-input soft-output iterative detectors/decoders. Soft-input information is added directly to incoming channel samples. Input signals comprising the received incoming channel samples with the added soft-input information are detected using a detector trellis. Branch metric terms are transformed to shift all time varying terms with the added soft-input information and some constant terms after an add compare select (ACS) unit. The shifted time varying terms with the added soft-input information and the shifted constant terms are added directly to state metric terms. The soft-input information is added directly to incoming channel samples and the computation of branch metrics is not affected. This allows optimization of a dual-max detector and soft-input soft-output Viterbi detector architectures to minimize hardware complexity and power consumption.

Abstract: Methods and apparatus for enhanced timing loop are provided for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). An acquisition timing circuit for generating an acquisition timing signal includes a plurality of compare functions for receiving and comparing consecutive input signal samples on an interleave with a threshold value. The acquisition timing circuit includes a majority rule voting function coupled to the plurality of compare functions for selecting a timing interleave. Tracking timing circuitry for generating a timing error signal during a read operation includes a channel data detector. The channel data detector receives disk signal input samples and includes a multiple-state path memory. The tracking timing circuit includes a low latency detector receiving disk signal input samples. A selector function is coupled to an output of the low latency detector and is coupled to the multiple-state path memory for selecting a state.

Abstract: Methods and apparatus are provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals using both partial matched filter and matched filter metrics. In the method of the invention, branch metric terms are transformed to shift all time varying terms and some constant terms after an add compare select (ACS) unit. The total number of non-zero constants on trellis branches is minimized. The shifted time varying terms and the shifted constant terms are added directly to state metric terms. The time varying terms are expressed as outputs Zn of a partial matched filter or as outputs Wn of a matched filter. For a given generalized partial response target, the time-invariance property of the Viterbi detector enables identifying the minimum number of non-zero constants on trellis branches without resorting to heuristics.

Abstract: Apparatus is provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed. The two-way add/compare/select includes a two-way compare for comparing first and second state metric input values and a pair of two-way adds in parallel with the two-way compare for respectively adding the first and second state metric input values with a second input value. The second input value includes a time varying term or a constant term. The time varying terms are expressed as outputs Zn of a partial matched filter or as outputs Wn of a matched filter. A multiplexer is coupled to the pair of two-way adds, the multiplexer receiving a selectable input controlled by the two-way compare. A pair of shifts coupled between the pair of two-way adds and the multiplexer receive a shift control input for providing metric bounding to avoid underflow.

Abstract: A combined read and write VCO for data channels is disclosed. The combined read and write VCO for data channels shares a common loop capacitor while providing optimal read and write VCO loop responses, and allows the VCO to relock to the write timebase after a read very quickly while maintaining an accurate timebase. The combined read and write VCO includes an oscillator providing an output signal having a frequency that varies proportionately to an oscillator input signal and an adjustable voltage source, the adjustable voltage source having a first configuration for a write mode and a second configuration for a read mode, and the adjustable voltage source providing the oscillator input signal to the oscillator in response to receiving an input current signal. The adjustable voltage source includes a first and second capacitor coupled in series and a switch coupled across the second capacitor, the switch being open to provide the first configuration and closed to provide the second configuration.

Abstract: Methods and apparatus are provided for detecting servo information in a direct access storage device. A plurality of data symbols are read from a disk to produce a readback signal. Each data symbol and each sequence of data symbols contains servo identification information. A correlation filter provides a matched filter function of an expected readback signal of the plurality of data symbols to produce a correlated readback signal. A threshold detector is coupled to the correlation filter for identifying a threshold signal representative of the data symbol. A data separator responsive to the threshold detector windows the threshold signal and provides clock and data signals. The data separator includes a digital variable frequency oscillator (VFO) which optimally centers incoming servo information from the disk in a timing window and provides standard clocked data for a servo processor. The threshold detector has a variable threshold voltage that is programmed using a trim digital-to-analog converter (DAC).

Abstract: A method and apparatus are provided for gain adjustment of a signal. A plurality of comparators compare the signal with a plurality of threshold values. An envelope detector coupled to the comparator includes a peak capture function for detecting the amplitude of the signal and a polarity memory for detecting polarity of the signal. A gain control function for setting a gain correction value is responsive to the peak capture function and the polarity memory. Features of the signal gain adjustment method and apparatus of the invention include an intelligent hold of the gain control over both thermal asperities and null gaps in the signal.