Abstract: An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided.

Abstract: A storage apparatus receives a first and second access requests for accessing items in a same clock cycle. The apparatus includes two stores, each storing a subset of the plurality of items, the first access request being routed to a first store and the second access request to a second store; miss detecting circuitry for detecting a miss in the accessed store; item retrieving circuitry for retrieving an item whose access generated a miss from a further store; updating circuitry for selecting an item to overwrite in one of the two stores, the updating circuitry being responsive to the miss detecting circuitry detecting the miss in an access to the first or second store and to at least one further condition to update both of the two stores with the item retrieved from the further store by overwriting the selected items.

Abstract: A processor is disclosed having a plurality of general purpose registers for storing data for processing by the processor; a set of system configuration registers for storing data indicative of a current configuration of the processor; the system configuration registers being located together in a register file; and at least some of the set of system configuration registers having a shadow register for storing a duplicate value remote from the register file, the shadow register being located close to a component that the shadow register stores a configuration value for.

Abstract: A processor 2 includes instruction decoding circuitry 8 and processing circuitry 16, 18, 20, 22, 24. The instruction decoding circuitry decodes at least one conditional program instruction in accordance with a conditional prediction as one of, in accordance with the condition prediction being a condition pass, one or more micro-operation instructions that control the processing circuitry to perform the processing action together with a condition resolution micro-operation instruction, or in accordance with the condition prediction being a condition fail, at least a condition resolution micro-operation instruction. Condition resolution circuitry 24 responds to the condition resolution micro-operation instruction to determine if the condition prediction is incorrect.

Abstract: A processor 2 includes an execution cluster 10 having multiple execution units 14, 16, 18, 20. The execution units 14, 16, 18, 20 share result buses 22, 24. Issue circuitry 12 within the execution cluster 10 determines future availability of a result bus 22, 24 for an instruction to be issued (or recently issued) using a known cycle count for that instruction. The availability is tracked for each result bus using a mask register 32 storing a mask value within which each bit position indicates the availability or non-availability of that result bus at a particular processing cycle in the future. The mask value is left shifted each processing cycle.

Abstract: A processor is disclosed having a plurality of general purpose registers for storing data for processing by the processor; a set of system configuration registers for storing data indicative of a current configuration of the processor; the system configuration registers being located together in a register file; and at least some of the set of system configuration registers having a shadow register for storing a duplicate value remote from the register file, the shadow register being located close to a component that the shadow register stores a configuration value for.

Abstract: An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided.

Abstract: A storage apparatus and method for storing a plurality of items is disclosed. The storage apparatus is configured to receive a first access request and a second access request for accessing respective items in a same clock cycle.

Abstract: A processor 2 includes an execution cluster 10 having multiple execution units 14, 16, 18, 20. The execution units 14, 16, 18, 20 share result buses 22, 24. Issue circuitry 12 within the execution cluster 10 determines future availability of a result bus 22, 24 for an instruction to be issued (or recently issued) using a known cycle count for that instruction. The availability is tracked for each result bus using a mask register 32 storing a mask value within which each bit position indicates the availability or non-availability of that result bus at a particular processing cycle in the future. The mask value is left shifted each processing cycle.

Abstract: A data processing system including multiple execution pipelines each having multiple execution stages E1, E2, E3 may have instructions issued together in parallel despite a data dependency therebetween if it is detected that the result operand value for the older instruction will be generated in an execution stage prior to an execution stage which requires that result operand value as an input operand value to the younger instruction and accordingly cross-forwarding of the operand value is possible between the execution pipelines to resolve the data dependency.

Abstract: A processor incorporates a branch prediction mechanism which acts to predict branch outcomes for predicted type branch instructions. The processor also supports non-predicted type branch instructions which are ignored by the branch prediction mechanism and are not subject to prediction. The impact of mispredictions degrading overall performance of the prediction mechanism is reduced by employing non-prediction type branch program instructions to represent/control branch operations when it is known that misprediction is likely for those branch operations.

Abstract: Techniques for preventing the loss of trace information being transmitted via trace infrastructure are disclosed. A data processing apparatus for processing instructions is provided.

Abstract: A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an instruction store for storing the sequence of instructions, and a processing unit for executing the sequence of instructions, the processing unit comprising at least a first processing path and a second processing path to enable at least two instructions of the sequence to be executed in parallel. When executing instructions in parallel, the first processing path executes an instruction which is earlier in the sequence than the instruction executing in the second processing path. The processing unit is operable when executing a multiple iteration instruction to allow a first iteration of the multiple iteration instruction to be executed in either the first processing path or the second processing path, but to cause all remaining iterations of the multiple iteration instruction to be executed in the first processing path.

Abstract: A data processing apparatus is provided having a plurality of functional units. At least one of the functional units is operable to perform data processing operations and at least a subset of the plurality of functional units have at least one of a respective co-processor register for storing configuration data and a respective debug register for storing debug data. A debug controller outputs debug data and co-ordinates debug operations. A configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units and a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. Separate provision of the debug ring-bus and the configuration ring-bus provides independent access to the co-processor register and to the debug register.

Abstract: A data processing system incorporates an instruction prefetch unit 8 including a static branch predictor 12. A static branch prediction cache 30, 32, 34 is provided for storing a most recently encountered static branch prediction such that a subsequent request to fetch the already encountered branch instruction can be identified before the opcode for that branch instruction is returned. The cached static branch prediction can thus redirect the prefetching to the branch target address sooner than the static predictor 12.

Abstract: An integrated circuit is provided with a tracing mechanism that is responsive to data access misses to insert a data place holder within a stream of trace data. When the missed data is later returned, this is inserted into the stream of traced data as a later data value. Analysis of the stream trace data may subsequently correlate between instructions that gave rise to data misses and the late data that was subsequently returned.

Abstract: A microprocessor integrated circuit 104 is provided with a trace controller 120 that is responsive to trace initiating conditions to trigger commencement of tracing operation and generation of a trace data stream. In the case of a multi-word data transfer instruction LSM, the trace controller 120 is able to trigger tracing partway through that instruction such that a subset of the transfer specified by that instruction are included within the trace data stream. All transfers subsequent to the triggering transfer may be traced with those transfers subsequent to the triggering transfer being marked with place holder codes rather than more informative full trace data for the triggering transfer.

Abstract: The present invention provides an apparatus and method for facilitating debugging of sequences of processing instructions. The apparatus comprises a processing circuit for executing processing instructions, the processing circuit having multiple states of operation, with each state of operation being assigned a context identifier to identify the state of operation. Further, logic is provided for facilitating debugging of sequences of processing instructions executed by the processing circuit. The logic comprises control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging, and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit.

Abstract: A data processing system incorporates an instruction prefetch unit 8 including a static branch predictor 12. A static branch prediction cache 30, 32, 34 is provided for storing a most recently encountered static branch prediction such that a subsequent request to fetch the already encountered branch instruction can be identified before the opcode before that branch instruction is returned. The cached static branch prediction can thus redirect the prefetching to the branch target address sooner than the static predictor 12.

Abstract: A data processing system incorporates an instruction prefetch unit 8 including a static branch predictor 12. A static branch prediction cache 30, 32, 34 is provided for storing a most recently encountered static branch prediction such that a subsequent request to fetch the already encountered branch instruction can be identified before the opcode before that branch instruction is returned. The cached static branch prediction can thus redirect the prefetching to the branch target address sooner than the static predictor 12.