Patents by Inventor David Jandzinski
David Jandzinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11765826Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: GrantFiled: January 25, 2021Date of Patent: September 19, 2023Assignee: Qorvo US, Inc.Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Publication number: 20210144853Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: ApplicationFiled: January 25, 2021Publication date: May 13, 2021Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Patent number: 10905007Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: GrantFiled: January 8, 2020Date of Patent: January 26, 2021Assignee: Qorvo US, Inc.Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Publication number: 20210007224Abstract: Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.Type: ApplicationFiled: January 8, 2020Publication date: January 7, 2021Inventors: John August Orlowski, Thomas Scott Morris, David Jandzinski
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Patent number: 10888040Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.Type: GrantFiled: August 28, 2018Date of Patent: January 5, 2021Assignee: Qorvo US, Inc.Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
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Patent number: 10882740Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: December 4, 2019Date of Patent: January 5, 2021Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
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Patent number: 10856456Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.Type: GrantFiled: August 28, 2018Date of Patent: December 1, 2020Assignee: Qorvo US, Inc.Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
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Patent number: 10773952Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: May 22, 2017Date of Patent: September 15, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
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Patent number: 10676348Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: May 22, 2017Date of Patent: June 9, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
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Publication number: 20200102217Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: ApplicationFiled: December 4, 2019Publication date: April 2, 2020Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, JR., Jonathan Hale Hammond
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Patent number: 10589993Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: May 22, 2017Date of Patent: March 17, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
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Patent number: 10549988Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: GrantFiled: May 22, 2017Date of Patent: February 4, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
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Publication number: 20190104653Abstract: The present disclosure relates to a shielded double-sided module, which includes a module substrate with a ground plane, at least one top electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a number of first module contacts attached to a bottom surface of the module substrate, a second mold compound, and a shielding structure. The second mold compound resides over the bottom surface of the module substrate, and each first module contact is exposed through the second mold compound. The shielding structure completely covers a top surface and a side surface of the module, and is electrically coupled to the ground plane within the module substrate.Type: ApplicationFiled: August 28, 2018Publication date: April 4, 2019Inventors: David Jandzinski, Thomas Scott Morris, Brian Howard Calhoun
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Patent number: 10043707Abstract: A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.Type: GrantFiled: March 26, 2013Date of Patent: August 7, 2018Assignee: Qorvo US, Inc.Inventors: John August Orlowski, David Jandzinski
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Patent number: 10020206Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: GrantFiled: June 3, 2016Date of Patent: July 10, 2018Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Patent number: 9997376Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: GrantFiled: June 3, 2016Date of Patent: June 12, 2018Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Patent number: 9960145Abstract: A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound residing on the top surface. A first mold compound is disposed on the top surface of the carrier. A first thinned flip chip die resides over a first portion of the first mold compound with interconnects extending through the first portion to the top surface wherein the first portion of the mold compound fills a region between the first flip chip die and the top surface. A second mold compound resides over the substrate and provides a first recess over the first flip chip die wherein the first recess extends to a first die surface of the first flip chip die. A third mold compound resides in the first recess and covers an exposed surface of the flip chip die.Type: GrantFiled: August 5, 2016Date of Patent: May 1, 2018Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Thomas Scott Morris, Jonathan Hale Hammond, David Jandzinski, Stephen Parker, Jon Chadwick
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Patent number: 9960054Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: GrantFiled: June 3, 2016Date of Patent: May 1, 2018Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Patent number: 9929024Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: GrantFiled: June 3, 2016Date of Patent: March 27, 2018Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Patent number: 9929125Abstract: A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound residing on the top surface. A first mold compound is disposed on the top surface of the carrier. A first thinned flip chip die resides over a first portion of the first mold compound with interconnects extending through the first portion to the top surface wherein the first portion of the mold compound fills a region between the first flip chip die and the top surface. A second mold compound resides over the substrate and provides a first recess over the first flip chip die wherein the first recess extends to a first die surface of the first flip chip die. A third mold compound resides in the first recess and covers an exposed surface of the flip chip die.Type: GrantFiled: August 5, 2016Date of Patent: March 27, 2018Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Thomas Scott Morris, Jonathan Hale Hammond, David Jandzinski, Stephen Parker, Jon Chadwick