Abstract: We describe a system for automatic setup of an audio/computer teleconference. The system comprises node units each having a phone connection, a telephone network connection, at least one computer network connection; and a system control server. The node unit comprises code to: transmit an outgoing audio announce message into a potential conference call via said telephone network audio connection, identifying the node unit; receive via the network audio connection an incoming audio announce message from a conference call to which the node unit is already connected; determine from the incoming message, an identifier for a remote node unit connecting to the conference call; and transmit to the server, via the computer network, identifiers for the local and remote node units. The server comprises code to: receive the node unit identifiers and provide computer equipment connection data to computer equipment at node.

Abstract: We describe a method of synchronizing a teleconference comprising audio carried on a telephone network and a digital data stream carried on a computer network. Audio at a first node is characterized to determine audio characterizing data. A digital data stream for the teleconference is also input at the first node and the audio characterizing data is inserted into the digital data stream and forwarded over the network. The audio and digital data streams are received separately at a second node of the system, and the audio characterizing data is extracted from the digital data stream and processed in conjunction with the received audio to determine a first-second node time offset. The audio and digital data streams are then synchronizing by adjusting, for example, a relative time delay of the received audio and digital streams at the second node responsive to the determined time offset.

Abstract: We describe a method of synchronising a teleconference comprising audio carried on a telephone network and a digital data stream carried on a computer network. Audio at a first node is characterised to determine audio characterising data. A digital data stream for the teleconference is also input at the first node and the audio characterising data is inserted into the digital data stream and forwarded over the network. The audio and digital data streams are received separately at a second node of the system, and the audio characterising data is extracted from the digital data stream and processed in conjunction with the received audio to determine a first-second node time offset. The audio and digital data streams are then synchronising by adjusting, for example, a relative time delay of the received audio and digital streams at the second node responsive to the determined time offset.

Abstract: We describe a system for automatic setup of an audio/computer teleconference. The system comprises node units each having a phone connection, a telephone network connection, at least one computer network connection; and a system control server. The node unit comprises code to: transmit an outgoing audio announce message into a potential conference call via said telephone network audio connection, identifying the node unit; receive via the network audio connection an incoming audio announce message from a conference call to which the node unit is already connected; determine from the incoming message, an identifier for a remote node unit connecting to the conference call; and transmit to the server, via the computer network, identifiers for the local and remote node units. The server comprises code to: receive the node unit identifiers and provide computer equipment connection data to computer equipment at node.

Abstract: A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states.

Abstract: A buffer is disclosed for storing data being transferred using a plurality of control channels, a data item of said data being transferred between a data source and a data destination using one of said plurality of control channels, said buffer comprising: a data input port operable to receive said data being transferred using said plurality of control channels; a data output port operable to output data to be transferred using said plurality of control channels; and a data store operable to store data received from said data input port prior to it being output by said data output port, said data store comprising a plurality of storage locations each operable to store a data item, said storage locations being arranged in groups, a storage location being allocated to a group in dependence on the control channel that a data item that it stores is received from, such that each group comprises storage locations storing data items received from a same one of said plurality of control channels.

Abstract: A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states.

Abstract: A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffers 34 are provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffers 34 are responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.

Abstract: A data processing apparatus comprises a master device 150, 160, 170, 180, a slave device 110, 120, 130 and a communication bus 140 via which transaction requests are passed from master to slave. A transaction annotator of the master device generates transaction identifiers having a master identifier portion and a priority request portion. The slave device determines an order of servicing of transaction requests in dependence upon transaction ordering requests at least partially derived from the master identifier portions and in dependence upon priority values specified in the priority request portions.

Abstract: The present invention provides a data processing apparatus and method for handling a multi-access instruction of the type which specifies that an access request of a first type and an access request of a second type should be performed without any intervening accesses taking place. The data processing apparatus has a processor operable to execute instructions, and a first master logic unit and a second master logic unit operable to process access requests generated during execution of those instructions. The access requests specify accesses to a slave device, with the first master logic unit being operable to access the slave device via a first bus, and the second master logic unit being operable to access the slave device via a second bus.

Abstract: A cache controller operable to control a cache comprising cache lines, each being operable to store data words and validity information indicating that all data words within that cache line are valid. The cache controller comprises a linefill mechanism operable to write data words to a cache line, to provide an indication when each of the data words has been written to the cache and to set the validity information when all data words in the cache line have been written; and a data word accessing mechanism, responsive to a request to access a data word during a linefill operation prior to the validity information being set, to determine from the indication provided by the linefill mechanism whether the data word to be accessed has already been written during the linefill operation and, if so, to provide a signal indicating that the data word is accessible.

Abstract: A cache controller (40, 60) operable to control a cache (30), the cache (30) comprising a plurality of cache lines, each of the plurality of cache lines being operable to store a plurality of data words and to store validity information indicating that all data words within that cache line are valid is provided.

Abstract: The present invention provides a data processing apparatus and method for handling a multi-access instruction of the type which specifies that an access request of a first type and an access request of a second type should be performed without any intervening accesses taking place. The data processing apparatus has a processor operable to execute instructions, and a first master logic unit and a second master logic unit operable to process access requests generated during execution of those instructions. The access requests specify accesses to a slave device, with the first master logic unit being operable to access the slave device via a first bus, and the second master logic unit being operable to access the slave device via a second bus.

Abstract: A data processing system is provided having a main processor 4 and a coprocessor 26. When in a debug mode, the main processor 4 and the coprocessor 26 are supplied with different instructions. The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.