Abstract: A programmable processor configured to perform one or more packet modifications through execution of one or more commands. A pipelined processor core comprises a first stage configured to selectively shift and mask data in each of a plurality of categories in response to one or more decoded commands, and combine the selectively shifted and masked data in each of the categories. The pipelined processor core further comprises a second stage configured to selectively perform one or more operations on the combined data from the first stage and other data responsive to the one or more decoded commands. In one implementation, the processor is implemented as an application specific integrated circuit (ASIC).

Abstract: A method of presenting different virtual routers to different end users, classes of service, or packets is provided. An incoming packet is received having a VLAN field and at least one additional field. A key is formed from the VLAN field and at least one other packet field, and mapped into a virtual router identifier (VRID) using an indirection mapping process. The VRID identifies a particular virtual router configuration from a plurality of possible virtual router configurations. A networking device is configured to have the particular virtual router configuration identified by the VRID, and the packet is then forwarded by the configured device.

Abstract: A method of presenting different virtual routers to different end users, classes of service, or packets is provided. An incoming packet is received having a VLAN field and at least one additional field. A key is formed from the VLAN field and at least one other packet field, and mapped into a virtual router identifier (VRID) using an indirection mapping process. The VRID identifies a particular virtual router configuration from a plurality of possible virtual router configurations. A networking device is configured to have the particular virtual router configuration identified by the VRID, and the packet is then forwarded by the configured device.

Abstract: A programmable processor configured to perform one or more packet modifications through execution of one or more commands. A pipelined processor core comprises a first stage configured to selectively shift and mask data in each of a plurality of categories in response to one or more decoded commands, and combine the selectively shifted and masked data in each of the categories. The pipelined processor core further comprises a second stage configured to selectively perform one or more operations on the combined data from the first stage and other data responsive to the one or more decoded commands. In one implementation, the processor is implemented as an application specific integrated circuit (ASIC).

Abstract: A programmable processor configured to perform one or more packet modifications through execution of one or more commands. A pipelined processor core comprises a first stage configured to selectively shift and mask data in each of a plurality of categories in response to one or more decoded commands, and combine the selectively shifted and masked data in each of the categories. The pipelined processor core further comprises a second stage configured to selectively perform one or more operations on the combined data from the first stage and other data responsive to the one or more decoded commands. In one implementation, the processor is implemented as an application specific integrated circuit (ASIC).

Abstract: A ring network with an automatic protection switching domain includes a control VLAN and at least one data VLAN. A master node in the ring is connected to at least one transit node. Each node in the ring network is linked to an adjacent node by a primary port or a secondary port. The master node receives notification of a fault via the control VLAN, the fault indicating a failed link between adjacent nodes. In response, the master node unblocks its secondary port to traffic on the data VLAN(s). The forwarding database entries on the master node and on the transit node(s) are flushed. Data traffic is flooded to the ring network until forwarding database entries on the master node and on the transit node(s) have been reestablished.

Abstract: Several systems for supporting packet processing are described. A first system supports virtual routing of a packet. A second system supports de-multiplexing of a packet. A third system supports advanced MPLS label processing of a packet.

Abstract: A system for statistically sampling packets is described. In this system, upon or after the occurrence of a predefined statistical event in relation to a packet, a pseudo-random value is obtained and compared to a predetermined threshold. Responsive to this comparison, the system selectively arranges to have the packet statistically sampled. A system for compiling statistics for packets undergoing processing by a packet processing system is described. In this system, upon or after the occurrence of a predefined statistical event in relation to a packet, a cumulative index for the packet is updated to reflect the current processing cycle for the packet. Upon or after completion of processing of the packet, whereupon the cumulative index may reflect more than one processing cycle, packet statistics are updated responsive to the cumulative index for the packet. A second system for compiling statistics for packets undergoing processing by a packet processing system is described.

Abstract: A method of presenting different virtual routers to different end users, classes of service, or packets is provided. An incoming packet is received having a VLAN field and at least one additional field. A key is formed from the VLAN field and at least one other packet field, and mapped into a virtual router identifier (VRID) using an indirection mapping process. The VRID identifies a particular virtual router configuration from a plurality of possible virtual router configurations. A networking device is configured to have the particular virtual router configuration identified by the VRID, and the packet is then forwarded by the configured device.

Abstract: In a packet processing system, where a packet processor normally performs a fixed number of processing cycles on a packet as it progresses through a processing pipeline, a method of extending the fixed number of processing cycles for a particular packet is provided. During the processing of a packet, an extension bit associated with the packet is set to an “on” state if extended processing of the packet is needed. While the extension bit is set to that state, updating of a count, indicating the number of processing cycles that has been undertaken for the packet, is inhibited. When the extended processing of the packet has been completed, the extension bit for the packet is set to an “off” state, and the updating of the count resumed. When that count indicates the number of processing cycles the packet has undergone equals or exceeds the fixed number, the packet is exited from the pipeline.

Abstract: A packet processing system architecture and method are provided. According to a first aspect of the invention, a plurality of quality of service indicators are provided for a packet, each with an assigned priority, and a configurable priority resolution scheme is utilized to select one of the quality of service indicators for assigning to the packet. According to a second aspect of the invention, wide data paths are utilized in selected areas of the system, while avoiding universal utilization of the wide data paths in the system. According to a third aspect of the invention, one or more stacks are utilized to facilitate packet processing. According to a fourth aspect of the invention, a packet size determiner is allocated to a packet from a pool of packet size determiners, and is returned to the pool upon or after determining the size of the packet.

Abstract: A MAC address detector for a networking device is provided, the device configured to present different virtual routers to different end users, classes of service or packets. First addressing logic provides a pool of N potential MAC addresses of the device, wherein N is an integer of one or more. Second addressing logic generates a (N+1)th potential MAC address of the device by combining a permanent or semi-permanent identifier of the device, for example, a chassis identifier, with a virtual router identifier determined responsive to the packet. Comparison logic indicates which if any of the (N+1) potential MAC addresses match the destination MAC address from the packet. Enable logic selectively activates responsive to the packet any of the (N+1) potential MAC addresses. Detection logic asserts a device address detection signal if any activated ones of the (N+1) potential MAC addresses match the destination address from the packet.

Abstract: A processor readable medium storing a data structure for supporting one or more packet modification operations is provided. The data structure has a pointer to a sequence of one or more commands stored in a first memory area and implementing one or more packet modification operations. The data structure also has a pointer to a burst of one or more data or mask items stored in a second memory area for use by the one or more commands. A method of performing one or more packet modification operations on a packet is also provided. This packet is associated with a data structure link. In this method, a data structure corresponding to the data structure link is retrieved. This data structure has the format described above. A packet modification system utilizing a data structure having this format is also provided.

Abstract: A method of providing virtual router functionality to a packet responsive to one or more abstracted virtual packet identifiers is provided. The method occurs in a networking device having a router core. The one or more abstracted virtual identifiers are abstracted from one or more virtual identifiers derived from the packet, thus insulating the router core from changes in the one or more virtual identifiers. A packet is received having a VLAN field, and a key is formed from the VLAN field and at least one other packet field. The key is mapped into an abstracted virtual identifier using an indirection mapping process. One or more core virtual router functions are then performed responsive to the abstracted virtual identifier.

Abstract: A packet processing system architecture and method are provided. According to a first aspect of the invention, packet parser functions are distributed throughout a packet processing system comprising a packet classification system and a packet modification system. According to a second aspect of the invention, an egress mirroring function is provided to the system. According to a third aspect of the invention, a multi-dimensional quality of service indicator for a packet is provided. According to a fourth aspect of the invention, a cascaded combination of multiple, replicated packet processing systems is used to process a packet. A fifth aspect of the invention involves any combination of one or more of the foregoing.

Abstract: Several systems for supporting packet processing are described. A first system supports virtual routing of a packet. A second system supports de-multiplexing of a packet. A third system supports advanced MPLS label processing of a packet.

Abstract: A pipelined packet processor is described having at least one pipeline, the at least one pipeline having one or more processing slots. Packets are assigned to available ones of the slots, and each of one or more of the assigned packets are processed during one or more cycles of processing. Upon or after a packet has undergone one or more cycles of processing, a packet classification or filtering decision is derived for the packet.

Abstract: Several systems for supporting packet processing are described. A first system supports virtual routing of a packet. A second system supports de-multiplexing of a packet. A third system supports advanced MPLS label processing of a packet.

Abstract: A packet parser is described that parses a packet by identifying the locations of respective packet layers. A staged approach to parsing the packet is employed whereby a first stage tests the packet data units within a first window for the presence of a first packet layer, and a second stage, at least partly in parallel with the first stage, tests the packet data units within a second overlapping window for the presence of a second packet layer. In response to an embedded packet comprising a first packet forming the payload portion of a second packet, the parser produces a data structure comprising first data that identifies the location of the first packet, second data that identifies the location of the second packet, third data that identifies one or more layers of the first packet, and fourth data that identifies one or more layers of the second packet.

Abstract: A ring network with an automatic protection switching domain includes a control VLAN and at least one data VLAN. A master node in the ring is connected to at least one transit node. Each node in the ring network is linked to an adjacent node by a primary port or a secondary port. The master node receives notification of a fault via the control VLAN, the fault indicating a failed link between adjacent nodes. In response, the master node unblocks its secondary port to traffic on the data VLAN(s). The forwarding database entries on the master node and on the transit node(s) are flushed. Data traffic is flooded to the ring network until forwarding database entries on the master node and on the transit node(s) have been reestablished.