Patents by Inventor David Kyong-sik Chung
David Kyong-sik Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8283982Abstract: An equalization circuit adjusts (e.g., equalizes) an input signal according to the value of one or more adjustment signals (e.g., equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.Type: GrantFiled: November 3, 2010Date of Patent: October 9, 2012Assignee: Broadcom CorporationInventors: David Kyong-Sik Chung, Afshin Momtaz
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Patent number: 7974337Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.Type: GrantFiled: October 27, 2009Date of Patent: July 5, 2011Assignee: Broadcom CorporationInventors: Afshin Momtaz, Mario Caresosa, David Kyong-Sik Chung, Davide Tonietto, Guangming Yin, Bruce Currivan, Thomas Kolze, Ichiro Fujimori
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Publication number: 20110044384Abstract: An equalization circuit adjusts (e.g., equalizes) an input signal according to the value of one or more adjustment signals (e.g., equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.Type: ApplicationFiled: November 3, 2010Publication date: February 24, 2011Applicant: BROADCOM CORPORATIONInventors: David Kyong-Sik Chung, Afshin Momtaz
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Patent number: 7839922Abstract: An equalization circuit adjusts (e.g., equalizes) an input signal according to the value of one or more adjustment signals (e.g., equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.Type: GrantFiled: May 18, 2004Date of Patent: November 23, 2010Assignee: Broadcom CorporationInventors: David Kyong-Sik Chung, Afshin Momtaz
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Patent number: 7088797Abstract: Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.Type: GrantFiled: September 10, 2002Date of Patent: August 8, 2006Assignee: Broadcom CorporationInventors: Afshin Momtaz, David Kyong-Sik Chung, Pang-Cheng Hsu
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Patent number: 7042271Abstract: A compensation apparatus maintains an effective resistance of one or more resistors in a circuit by associating an adjustable resistor circuit to each resistor. The compensation apparatus compares the resistance of a resistor in the circuit with the resistance of a reference resistor. When the resistance of the resistor in the circuit falls outside of a desired range, the compensation apparatus adjusts the resistance of the adjustable resistor to adjust the effective resistance of the resistor and adjustable resistor combination.Type: GrantFiled: May 6, 2004Date of Patent: May 9, 2006Assignee: Broadcom CorporationInventors: David Kyong-Sik Chung, Afshin Momtaz, Mario Caresosa
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Patent number: 6982604Abstract: A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating the count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.Type: GrantFiled: November 2, 2004Date of Patent: January 3, 2006Assignee: Broadcom CorporationInventor: David Kyong-sik Chung
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Patent number: 6833763Abstract: A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating their count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.Type: GrantFiled: April 22, 2004Date of Patent: December 21, 2004Assignee: Broadcom CorporationInventor: David Kyong-sik Chung
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Publication number: 20040196106Abstract: A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating their count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.Type: ApplicationFiled: April 22, 2004Publication date: October 7, 2004Applicant: Broadcom CorporationInventor: David Kyong-sik Chung
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Patent number: 6747518Abstract: A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating their count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.Type: GrantFiled: December 30, 2002Date of Patent: June 8, 2004Assignee: Broadcom CorporationInventor: David Kyong-sik Chung
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Publication number: 20040047440Abstract: Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.Type: ApplicationFiled: September 10, 2002Publication date: March 11, 2004Applicant: Broadcom CorporationInventors: Afshin Momtaz, David Kyong-Sik Chung, Pang-Cheng Hsu
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Patent number: 5861766Abstract: A frequency synthesizer has multiple modes of operation including a relatively short-duration frequency seek mode and a relatively long-duration normal mode. The synthesizer responds to a reference frequency signal and produces a periodic signal at a frequency that is a rational number times the frequency of the reference frequency signal. The synthesizer comprises a VCO, a feedforward state machine, a feedback state machine, a phase comparator, controllable gain circuitry between the phase comparator and the VCO, and logic circuitry that coordinates the operation of the feedforward and feedback state machines during the seek mode.Type: GrantFiled: April 17, 1997Date of Patent: January 19, 1999Assignee: Western Digital CorporationInventors: Howard Anthony Baumer, David Kyong-sik Chung, Gerald Weslie Shearer