Abstract: Magazine block device for firearm dry fire practice which allows a user to practice proper firearm handling skills without expending ammunition, including recocking and actuating the firearm slide without pressing the slide lock release. In an aspect, a magazine block device is provided having a bullet-shaped body, two upper ridges forming a longitudinal channel through which the firearm breach face loading tab may pass without dislodging the magazine block device, and an offset lower ridge. The lower ridge is configured to evenly force a magazine follower down a sufficient distance to prevent actuation of the firearm slide lock. This allows dry fire practice of pulling the slide. Several other features include ridges to assist a user to remove and load the block device in and out of a magazine, as well as a pocket to mechanically remove same.

Abstract: Magazine block device for firearm dry fire practice which allows a user to practice proper firearm handling skills without expending ammunition, including recocking and actuating the firearm slide without pressing the slide lock release. In an aspect, a magazine block device is provided having a bullet-shaped body, two upper ridges forming a longitudinal channel through which the firearm breach face loading tab may pass without dislodging the magazine block device, and an offset lower ridge. The lower ridge is configured to evenly force a magazine follower down a sufficient distance to prevent actuation of the firearm slide lock. This allows dry fire practice of pulling the slide. Several other features include ridges to assist a user to remove and load the block device in and out of a magazine, as well as a pocket to mechanically remove same.

Abstract: A method and system for providing remote access to the facilities of a server computer are provided. A site integration application programming interface at a co-branded Web site. The site integration application programming interface exposes a number of servlets that may be executed in response to requests received from a business partner Web site over a secure communications link. The servlets provide functionality for accessing the user registration and deletion facilities of the co-branded Web site. Moreover, the servlets also provide access to other administrative facilities provided at the co-branded Web site. The servlets also provide functionality for authorizing a user to access the co-branded we site. This servlet may be executed in conjunction with the login facilities of the business partner web site to permit concurrent login at both sites.

Abstract: A method and system for providing remote access to the facilities of a server computer are provided. A site integration application programming interface at a co-branded Web site. The site integration application programming interface exposes a number of servlets that may be executed in response to requests received from a business partner Web site over a secure communications link. The servlets provide functionality for accessing the user registration and deletion facilities of the co-branded Web site. Moreover, the servlets also provide access to other administrative facilities provided at the co-branded Web site. The servlets also provide functionality for authorizing a user to access the co-branded we site. This servlet may be executed in conjunction with the login facilities of the business partner web site to permit concurrent login at both sites.

Abstract: An on-line database updating network system and method using object-oriented programming to build a program of discrete blocks, with each block being separately accessible, modifiable, and replaceable. The system includes a user terminal, a host terminal, and a communications channel. Origin dates of user module blocks of information stored in the user terminal are compared, over the communications channel, with origin dates of corresponding host module blocks of information stored in the host terminal. Host module blocks having origin dates more recent than corresponding user module blocks are downloaded as updated blocks over the communications channel to the user terminal. The downloaded updated blocks are then used to update the relevant user module blocks of information. Alternate host terminals may also be accessed by the user terminal, and updated alternate host module blocks of information may be downloaded to the user terminal.

Abstract: An information distribution program (36) is provided for automatically distributing information over a network (24) connecting a plurality of computers (15). Each computer (15) is installed with the information distribution program (36), which comprises a family construction module (44), a publication module (40), a subscription module (42), and an information tree (46). The information tree (46) stores the most recent information available to the computer (15). The family construction module (44) organizes the various computers (15) connected to the network (24) into immediate and extended families of related computers (15). The publication module (40) automatically distributes, “publishes” or “pushes” the information to the immediate and extended family members of a computer (15) which have shown an interest in the information.

Abstract: An information distribution program (36) is provided for automatically distributing information over a network (24) connecting a plurality of computers (15). Each computer (15) is installed with the information distribution program (36), which comprises a family construction module (44), a publication module (40), a subscription module (42), and an information tree (46). The information tree (46) stores the most recent information available to the computer (15). The family construction module (44) organizes the various computers (15) connected to the network (24) into immediate and extended families of related computers (15). The publication module (40) automatically distributes, “publishes” or “pushes” the information to the immediate and extended family members of a computer (15) which have shown an interest in the information.

Abstract: An information distribution program (36) is provided for automatically distributing information over a network (24) connecting a plurality of computers (15). Each computer (15) is installed with the information distribution program (36), which comprises a family construction module (44), a publication module (40), a subscription module (42), and an information tree (46). The information tree (46) stores the most recent information available to the computer (15). The family construction module (44) organizes the various computers (15) connected to the network (24) into immediate and extended families of related computers (15). The publication module (40) automatically distributes, “publishes” or “pushes” the information to the immediate and extended family members of a computer (15) which have shown an interest in the information.

Abstract: An on-line database updating network system and method using object-oriented programming to build a program of discrete blocks, with each block being separately accessible, modifiable, and replaceable. The system includes a user terminal, a host terminal, and a communications channel. Origin dates of user module blocks of information stored in the user terminal are compared, over the communications channel, with origin dates of corresponding host module blocks of information stored in the host terminal. Host module blocks having origin dates more recent than corresponding user module blocks are downloaded as updated blocks over the communications channel to the user terminal. The downloaded updated blocks are then used to update the relevant user module blocks of information. Alternate host terminals may also be accessed by the user terminal, and updated alternate host module blocks of information may be downloaded to the user terminal.

Abstract: An on-line database updating network system and method using object-oriented programming to build a program of discrete blocks, with each block being separately accessible, modifiable, and replaceable. The system includes a user terminal, a host terminal, and a communications channel. Origin dates of user module blocks of information stored in the user terminal are compared, over the communications channel, with origin dates of corresponding host module blocks of information stored in the host terminal. Host module blocks having origin dates more recent than corresponding user module blocks are downloaded as updated blocks over the communications channel to the user terminal. The downloaded updated blocks are then used to update the relevant user module blocks of information. Alternate host terminals may also be accessed by the user terminal, and updated alternate host module blocks of information may be downloaded to the user terminal.

Abstract: An output driver including pull-up and pull-down output transistors is formed in a silicon substrate. The source and the drain of the pull-up output transistor are formed in a common bulk region of the substrate. A bulk potential control circuit for controlling the voltage of the bulk region, a resistive element and a gate drive control circuit are also formed in the silicon substrate. A layer of interconnect formed over a top surface of the silicon substrate may selectively couple into the output driver circuit one or more of the resistive element between a source of the pull-down output transistor and a reference voltage source, the bulk potential control circuit to control the voltage of the bulk region of the silicon substrate, and the gate drive control circuit to control the rate of change of voltage on the gate of the pull-down transistor as a function of the voltage on this gate.

Abstract: A hysteresis circuit comprises a first logic section, a second logic section cascaded with the first logic section, and circuitry for controlling hysteresis threshold voltages of the hysteresis circuit. The hysteresis controlling circuitry conducts current from a source of a first supply voltage to the output lead of the first logic section during a low-to-high transition of an input voltage on an input terminal of the hysteresis circuit. The hysteresis controlling circuitry conducts current from the output lead of the first logic section to a source of a second supply voltage during a high-to-low transition of the input voltage on the input terminal of the hysteresis circuit. A clock generator integrated circuit chip employing the hysteresis circuit in a voltage controlled oscillator can generate squarewave signals of 150 MHz onto a plurality of output terminals when powered from approximately 3.3 volts throughout a 0 to 70 degree Celsius temperature range, a clock skew of less than 0.

Abstract: An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising a pullup field effect transistor (FET) and a like-polarity pulldown FET. The two pullup and pulldown FETs are coupled in series between two voltage supply lines. In one aspect of the invention, the output driver comprises a charge rate control circuit which charges the gate of the pulldown FET when the pulldown FET is to be turned on so that the voltage on the gate increases at a first rapid rate and then increases at a second slower rate after the pulldown FET begins to conduct current. In another aspect of the invention, a resistive element is provided between the source of the pulldown FET and a ground voltage supply line.

Abstract: A hysteresis circuit comprises a first logic section, a second logic section cascaded with the first logic section, and circuitry for controlling hysteresis threshold voltages of the hysteresis circuit. The hysteresis controlling circuitry conducts current from a source of a first supply voltage to the output lead of the first logic section during a low-to-high transition of an input voltage on an input terminal of the hysteresis circuit. The hysteresis controlling circuitry conducts current from the output lead of the first logic section to a source of a second supply voltage during a high-to-low transition of the input voltage on the input terminal of the hysteresis circuit. A clock generator integrated circuit chip employing the hysteresis circuit in a voltage controlled oscillator can generate squarewave signals of 150 MHz onto a plurality of output terminals when powered from approximately 3.3 volts throughout a 0 to 70 degree Celsius temperature range, a clock skew of less than 0.

Abstract: A leadframe for use in an integrated circuit package is described. The leadframe comprises a plurality of electrically conductive leads, a die attach pad, and an electrically conductive ring or rings formed generally around the circumference of the die attach pad and between the die attach pad and leads. In one embodiment, at least one of the leads is formed integrally with each ring. The die attach pad may also be formed integrally with one or more leads. In another embodiment, the ring or rings are formed so that they are electrically isolated from the die attach pad, and the die attach pad, leads, and ring or rings are all formed in substantially the same plane. In some embodiments, the ring or rings are broken into electrically isolated sections. Each of the ring sections (and die attach pad, if appropriate) may be electrically connected to a voltage source outside the integrated circuit package (e.g., a power supply or ground).

Abstract: An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising a pullup field effect transistor (FET) and a like-polarity pulldown FET. The two pullup and pulldown FETs are coupled in series between two voltage supply lines. In one aspect of the invention, the output driver comprises a charge rate control circuit which charges the gate of the pulldown FET when the pulldown FET is to be turned on so that the voltage on the gate increases at a first rapid rate and then increases at a second slower rate after the pulldown FET begins to conduct current. In another aspect of the invention, a resistive element is provided between the source of the pulldown FET and a ground voltage supply line.

Abstract: In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma/nsec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode.

Abstract: A pipeline memory access circuit has a memory address buffer for buffering memory addresses. The buffer has a first and a second pass gate, and each of the pass gates has a pair of complementary metal-oxide-semiconductor (CMOS) transistors. An apparatus is provided for selectively switching the buffer between an asynchronous and a synchronous mode of operation. The switching apparatus includes circuits for alternately opening and closing the first and second pass gates when the buffer is in its synchronous mode of operation and for simultaneously opening both of the pass gates when the buffer is in its asynchronous mode of operation.

Abstract: In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma/nsec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse bias potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode.

Abstract: A leadframe for use in an integrated circuit package is described. The leadframe comprises a plurality of electrically conductive leads, a die attach pad, and an electrically conductive ring or rings formed generally around the circumference of the die attach pad and between the die attach pad and leads. In one embodiment, at least one of the leads is formed integrally with each ring. The die attach pad may also be formed integrally with one or more leads. In another embodiment, the ring or rings are formed so that they are electrically isolated from the die attach pad, and the die attach pad, leads, and ring or rings are all formed in substantially the same plane. In some embodiments, the ring or rings are broken into electrically isolated sections. Each of the ring sections (and die attach pad, if appropriate) may be electrically connected to a voltage source outside the integrated circuit package (e.g., a power supply or ground).