Patents by Inventor David L. DeMaris
David L. DeMaris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8863044Abstract: Candidate layout patterns can be assessed using a sparse pattern dictionary of known design layout patterns by determining sparse coefficients for each candidate pattern, reconstructing the respective candidate pattern, and determining reconstruction error. Any pattern with reconstruction error over a threshold value can be flagged. Compressive sampling can be employed, such as by projecting each candidate pattern onto a random line or a random matrix. The dictionary can be built by determining sparse coefficients of known patterns and respective basis function sets using matching pursuit, variants of SVD, and/or other techniques.Type: GrantFiled: September 6, 2013Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Nathalie Casati, David L. DeMaris, Frank De Morsier, Virginia Estellers Casas, Maria Gabrani
-
Patent number: 8667427Abstract: A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.Type: GrantFiled: February 23, 2012Date of Patent: March 4, 2014Assignee: International Business Machines CorporationInventors: David L. DeMaris, Maria Gabrani, Ekaterina Volkova
-
Patent number: 8661370Abstract: A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.Type: GrantFiled: August 24, 2012Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: David L DeMaris, Maria Gabrani, Ekaterina Volkova
-
Publication number: 20120324406Abstract: A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.Type: ApplicationFiled: August 24, 2012Publication date: December 20, 2012Applicant: International Business Machines CorporationInventors: David L. DeMaris, Maria Gabrani, Ekaterina Volkova
-
Publication number: 20120221984Abstract: A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.Type: ApplicationFiled: February 23, 2012Publication date: August 30, 2012Applicant: International Business CorporationInventors: David L. DeMaris, Maria Gabrani, Ekaterina Volkova
-
Patent number: 8234603Abstract: The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate ?i of spatial frequency space, an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate ?i, a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate ?i, and a total energy entropy factor comprising total energy entropy of said diffraction orders. The hard-to-print energy includes energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=1, and the easy-to-print energy includes energy of the diffraction orders located at intermediate values of normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=1.Type: GrantFiled: July 14, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Saeed Bagheri, David L. DeMaris, Maria Gabrani, David Osmond Melville, Alan E. Rosenbluth, Kehan Tian
-
Patent number: 8201132Abstract: A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.Type: GrantFiled: December 7, 2009Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: David L. DeMaris, Timothy G. Dunham, William C. Leipold, Daniel N. Maynard, Michael E. Scaman, Shi Zhong
-
Publication number: 20120017194Abstract: The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate ?i spatial frequency space, an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate ?i, a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate ?i, and a total energy entropy factor comprising total energy entropy of said diffraction orders. The hard-to-print energy includes energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=1, and the easy-to-print energy includes energy of the diffraction orders located at intermediate values of normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=1.Type: ApplicationFiled: July 14, 2010Publication date: January 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Saeed Bagheri, David L. DeMaris, Maria Gabrani, David Osmond Melville, Alan E. Rosenbluth, Kehan Tian
-
Publication number: 20100095254Abstract: A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.Type: ApplicationFiled: December 7, 2009Publication date: April 15, 2010Inventors: David L. DeMaris, Timothy G. Dunham, William C. Leipold, Daniel N. Maynard, Michael E. Scaman, Shi Zhong
-
Patent number: 7685544Abstract: A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.Type: GrantFiled: November 29, 2007Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: David L. DeMaris, Timothy G. Dunham, William C. Leipold, Daniel N. Maynard, Michael E. Scaman, Shi Zhong
-
Patent number: 7552417Abstract: Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region.Type: GrantFiled: June 4, 2008Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: Bette L. Bergman Reuter, David L. DeMaris, Mark A. Lavin, William C. Leipold, Daniel N. Maynard, Maharaj Mukherjee
-
Publication number: 20080320421Abstract: A system, method and program product for searching and classifying patterns in a VLSI design layout. A method is provided that includes generating a target vector using a two dimensional (2D) low discrepancy sequence; identifying layout regions in a design layout; generating a feature vector for a layout region; comparing a subset of sequence values in the target vector with sequence values in the feature vector as an initial filter, wherein the system for comparing determines that the layout region does not contain a match if a comparison of the subset of sequence values in the target vector with sequence values in the feature vector falls below a threshold; and outputting search results.Type: ApplicationFiled: June 20, 2007Publication date: December 25, 2008Inventors: David L. Demaris, Rouwaida N. Kanj, Daniel N. Maynard, Michael D. Monkowski
-
Publication number: 20080247633Abstract: A system of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.Type: ApplicationFiled: May 9, 2008Publication date: October 9, 2008Inventors: David L DeMaris, Mark A. Lavin, William C. Leipold, Daniel N. Maynard, Maharaj Mukherjee
-
Publication number: 20080232675Abstract: Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region.Type: ApplicationFiled: June 4, 2008Publication date: September 25, 2008Applicant: International Business Machines CorporationInventors: Bette L. Bergman Reuter, David L. DeMaris, Mark A. Lavin, William C. Leipold, Daniel N. Maynard, Maharaj Mukherjee
-
Patent number: 7415695Abstract: Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region.Type: GrantFiled: May 15, 2007Date of Patent: August 19, 2008Assignee: International Business Machines CorporationInventors: Bette L. Bergman Reuter, David L. DeMaris, Mark A. Lavin, William C. Leipold, Daniel N. Maynard, Maharaj Mukherjee
-
Patent number: 7404174Abstract: A method of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.Type: GrantFiled: July 27, 2004Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: David L. DeMaris, Mark A. Lavin, William C. Leipold, Daniel N. Maynard, Maharaj Mukherjee
-
Patent number: 7353472Abstract: A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.Type: GrantFiled: August 12, 2005Date of Patent: April 1, 2008Assignee: International Business Machines CorporationInventors: David L. DeMaris, Timothy G. Dunham, William C. Leipold, Daniel N. Maynard, Michael E. Scaman, Shi Zhong
-
Patent number: 7284230Abstract: Disclosed is a method of locating systematic defects in integrated circuits. Extracting and index processing of a circuit design and feature searching are performed. During extracting and index processing, a window grid for the circuit design is established and basis patterns are merged with shapes within each. Shapes in each window are transformed into feature vectors by finding intersections between basis patterns and shapes. Feature vectors are clustered to produce an index of feature vectors. During feature searching, a defect region window of the circuit layout is identified and basis patterns are merged with shapes in the defect region window. Shapes in the defect region window are transformed into defect vectors by finding intersections between basis patterns and shapes. Feature vectors similar to the defect vector are found using representative feature vectors from the index of feature vectors. Similarities and differences between defect vectors and feature vectors are analyzed.Type: GrantFiled: October 30, 2003Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Bette L. Bergman Reuter, David L. DeMaris, Mark A. Lavin, William C. Leipold, Daniel N. Maynard, Maharaj Mukherjee