Abstract: A method of adjusting clock skew for a computer system, wherein the computer system includes a clock generator for generating a clock signal, at least one logic module and a clock distribution network for carrying the clock signal from the clock generator to the logic modules, includes deskewing each of the logic modules and also deskewing the distribution network between the clock generator and the logic modules. Deskewing is performed by measuring a delay for the clock signal between a clock input and a test point on the logic module, comparing the measured delay to a desired delay, calculating an amount of adjustment needed to cause the measure delay to equal a desired delay and programming a skew compensator on the logic module with a calculator to mount adjustment.

Abstract: An apparatus for adjusting signal delay includes an input for receiving a signal to be delay adjusted. A delay circuit is connected to the input means for providing a plurality of selectable signal paths for various delay amounts for producing a delay adjusted signal therefrom. A delay selection circuit is connected to the delay circuit for selecting the signal path so as to select a delay amount and an output provides the delay adjusted signal to a load. Skew compensation is employed on the input and individually on each output to compensate for clock distribution network skew and intracircuit skews, respectively.

Abstract: An apparatus precisely adjusts the delay of a clock signal so as to reduce clock skew. The electronically programmable skew adjustment can be self-contained within a single IC package. The apparatus has an input for receiving a signal to be delay adjusted, delay elements including capacitive delay elements for providing multiple signal paths of various delays, delay selection circuitry for selecting the signal paths so as to select a delay amount, and an output to provide the delay adjusted signal to a load.

Abstract: A ceramic chip carrier package for integrated circuits is described which provides reduced interlead capacitance. A cavity for the placement of the integrated circuit chip is centrally located on a substrate. The leads of the package are bridged between the cavity and the outer periphery of the substrate. The leads are bonded to the substrate using adhesive glass placed on the substrate at the outer periphery of the cavity and at the outer periphery of the substrate. Sealing glass is placed on the outer periphery of the substrate over the leads to provide a bonding material for a lid to the package. The area between the cavity and the outer periphery of the substrate has no adhesive or sealing glass which thus provides an air dielectric between the leads so that interlead capacitance is reduced.