Patents by Inventor David L. Roper
David L. Roper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7656678Abstract: The present invention stacks integrated circuit packages into circuit modules. In a preferred embodiment, solder paste and primary adhesive respectively are applied to selected locations on the flex circuitry. Supplemental adhesive is applied to additional locations on the flex circuitry, CSP, or other component. The flex circuitry and the CSP are brought into proximity with each other. During solder reflow operation, a force is applied and the CSP collapses toward the flex circuitry, displacing the primary adhesive and the supplemental adhesive. The supplemental adhesive establishes a bond providing additional support to the flex circuitry. In another embodiment, CSPs or other integrated circuit packages are bonded to each other or to other components with a combination of adhesives. A rapid bond adhesive maintains alignment of the bonded packages and/or components during assembly, and a structural bond adhesive provides additional strength and/or structural integrity to the bond.Type: GrantFiled: October 31, 2005Date of Patent: February 2, 2010Assignee: Entorian Technologies, LPInventors: Julian Partridge, James Douglas Wehrly, Jr., David L. Roper, Joseph Villani
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Patent number: 7626273Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.Type: GrantFiled: January 20, 2009Date of Patent: December 1, 2009Assignee: Entorian Technologies, L.P.Inventors: Julian Partridge, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr.
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Patent number: 7606048Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).Type: GrantFiled: October 5, 2004Date of Patent: October 20, 2009Assignee: Enthorian Technologies, LPInventors: James W. Cady, James Wilder, David L. Roper, Russell Rapport, James Douglas Wehrly, Jr., Jeffrey Alan Buchle
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Patent number: 7595550Abstract: A form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design that is disposed about the form. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.Type: GrantFiled: July 1, 2005Date of Patent: September 29, 2009Assignee: Entorian Technologies, LPInventors: James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr.
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Patent number: 7586758Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).Type: GrantFiled: October 5, 2004Date of Patent: September 8, 2009Assignee: Entorian Technologies, LPInventors: James W. Cady, James Wilder, David L. Roper, Russell Rapport, James Douglas Wehrly, Jr., Jeffrey Alan Buchle
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Publication number: 20090160042Abstract: A system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along an obverse side of a flex circuit. In a preferred embodiment, the lower surface of the body of the leaded packaged IC contacts the surface of the flex circuitry. The semiconductor die is disposed beneath the leaded package IC and, in preferred embodiments, disposed in a window that passes through at least a part of the flex circuitry and is attached to a conductive layer of the flex circuitry. In other embodiments, the semiconductor die is attached to the body of the leaded packaged IC. The flex circuitry preferably employs at least two conductive layers and, in preferred embodiments, the leaded packaged IC is connected to the flex circuitry at one layer while the semiconductor die is connected to the flex circuitry at the other conductive layer.Type: ApplicationFiled: March 2, 2009Publication date: June 25, 2009Inventors: James Douglas Wehrly, JR., Leland Szewerenko, David L. Roper
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Patent number: 7542304Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.Type: GrantFiled: March 19, 2004Date of Patent: June 2, 2009Assignee: Entorian Technologies, LPInventors: Russell Rapport, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr., Jeff Buchle
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Publication number: 20090124045Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.Type: ApplicationFiled: January 20, 2009Publication date: May 14, 2009Inventors: Julian Partridge, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, JR.
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Patent number: 7524703Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.Type: GrantFiled: September 7, 2005Date of Patent: April 28, 2009Assignee: Entorian Technologies, LPInventors: James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr.
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Patent number: 7522421Abstract: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. A rigid substrate configured with wings diverging from a central axis to create, preferably, a āVā-shaped structure provide supportive structure for the populated flex circuitry that is wrapped about an edge of the substrate.Type: GrantFiled: July 13, 2007Date of Patent: April 21, 2009Assignee: Entorian Technologies, LPInventors: David L. Roper, Douglas Wehrly, Jr., Mark Wolfe
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Patent number: 7508069Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.Type: GrantFiled: May 18, 2006Date of Patent: March 24, 2009Assignee: Entorian Technologies, LPInventors: James Douglas Wehrly, Jr., Ron Orris, Leland Szewerenko, Tim Roy, Julian Partridge, David L. Roper
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Publication number: 20090073661Abstract: A circuit module includes a printed circuit board (PCB) having a first side, a second side, and a bottom perimeter edge. The PCB exhibits a first thickness along the bottom perimeter edge. The first side includes a recessed area and, in that recessed area, the PCB has a second thickness that is less than the first thickness. A plurality of integrated circuits (ICs) are fixed to the PCB in the recessed area. A plurality of module contacts are connected to the ICs and are disposed along at least one of the first and second sides and are configured to provide electrical connection between the circuit module and an edge connector.Type: ApplicationFiled: September 18, 2007Publication date: March 19, 2009Applicant: STAKTEK GROUP L.P.Inventors: Mark Wolfe, James Wilder, David L. Roper
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Patent number: 7495334Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with flex circuitry. A form standard is disposed between the flex circuitry and a CSP in the stack. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent CSPs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a thermally conductive physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.Type: GrantFiled: August 4, 2005Date of Patent: February 24, 2009Assignee: Entorian Technologies, LPInventors: Russell Rapport, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr., Jeff Buchle, Julian Dowden
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Patent number: 7485951Abstract: An IC die and a flexible circuit structure are integrated into a lower stack element that can be stacked with either further integrated lower stack element iterations or with pre-packaged ICs in any of a variety of package types. The present invention may be employed to stack similar or dissimilar integrated circuits and may be used to create modularized systems. In a preferred embodiment, a die is positioned above the surface of portions of a pair of flex circuits. Connection is made between the die and the flex circuitry. A protective layer such as a molded plastic, for example, is formed to protect the flex-connected die and its connection to the flex. Connective elements are placed along the flex circuitry to create an array of module contacts along the second side of the flex circuitry. The flex circuitry is positioned above the body-protected die to create an integrated lower stack element.Type: GrantFiled: May 9, 2003Date of Patent: February 3, 2009Assignee: Entorian Technologies, LPInventors: David L. Roper, Curtis Hart, James Wilder, Phill Bradley, James G. Cady, Jeff Buchle, James Douglas Wehrly, Jr.
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Publication number: 20080211077Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers.Type: ApplicationFiled: May 11, 2006Publication date: September 4, 2008Inventors: James W. Cady, Julian Partridge, James Douglas Wehrly, James Wilder, David L. Roper, Jeffrey Alan Buchle
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Patent number: 7335975Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements.Type: GrantFiled: October 5, 2004Date of Patent: February 26, 2008Assignee: Staktek Group L.P.Inventors: James W. Cady, James Wilder, David L. Roper, Russell Rapport, James Douglas Wehrly, Jr., Jeffrey Alan Buchle
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Patent number: 7304382Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.Type: GrantFiled: May 18, 2006Date of Patent: December 4, 2007Assignee: Staktek Group L.P.Inventors: James Douglas Wehrly, Jr., Ron Orris, Leland Szewerenko, Tim Roy, Julian Partridge, David L. Roper
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Patent number: 7256484Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.Type: GrantFiled: October 12, 2004Date of Patent: August 14, 2007Assignee: Staktek Group L.P.Inventors: Russell Rapport, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr., Jeff Buchle
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Publication number: 20070164416Abstract: A system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along an obverse side of a flex circuit. In a preferred embodiment, the lower surface of the body of the leaded packaged IC contacts the surface of the flex circuitry. The semiconductor die is disposed beneath the leaded package IC and, in preferred embodiments, disposed in a window that passes through at least a part of the flex circuitry and is attached to a conductive layer of the flex circuitry. In other embodiments, the semiconductor die is attached to the body of the leaded packaged IC. The flex circuitry preferably employs at least two conductive layers and, in preferred embodiments, the leaded packaged IC is connected to the flex circuitry at one layer while the semiconductor die is connected to the flex circuitry at the other conductive layer.Type: ApplicationFiled: June 7, 2006Publication date: July 19, 2007Inventors: James Douglas Wehrly, Leland Szewerenko, David L. Roper
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Publication number: 20070158821Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along one side of a flex circuit. The semiconductor die is disposed along the flex circuitry and preferably is between at least a part of the flex circuitry and the body of the leaded packaged IC. Preferably, the die is attached to a conductive layer of the flex circuitry. The flex circuitry preferably employs at least two conductive layers and the leaded packaged IC and die are preferably connected to one of the conductive layers of the flex circuitry. In preferred modules, the leaded packaged IC is preferably a flash memory device and the semiconductor die is preferably a controller.Type: ApplicationFiled: July 7, 2006Publication date: July 12, 2007Inventors: Leland Szewerenko, James Douglas Wehrly, David L. Roper