Abstract: A video signal processor includes a stored-program controller which concurrently reads two instruction values from a program memory during each instruction cycle. The next instruction used by the video signal processor is selected from between these two values. If the current instruction indicates a conditional branch operation, the value of one of a plurality of conditions internal to the video signal processor determines which of these two instructions is selected. Otherwise, a value provided by the current instruction itself determines which of the two instructions is selected. This configuration of the stored program controller implements a conditional branch facility in which there is no delay in fetching an instruction for either value of the selected condition.

Abstract: A parallel-pipeline video signal processing system is disclosed which includes a statistical decoder, an arithmetic and logic unit and a pixel interpolator which operate in parallel under the control of sequencing circuitry to expand a compressed video signal. The video signal may have been developed using a variety of compression techniques including Huffman-type statistical encoding.

Abstract: A processor for expanding a compressed video signal includes a pixel interpolator which interpolates between input pixel values in two dimensions. This interpolator calculates and stores intermediate pixel values which are interpolated in the vertical direction. A pair of these intermediate pixel values are then fed back into the interpolator which performs a horizontal interpolation to produce pixel values that are interpolated in both the horizontal and vertical dimensions. In steady state operation, the horizontal and vertical interpolation operations are alternated to produce a stream of two-dimensionally interpolated values.

Abstract: A display processor for a computer with graphics capability includes color map memories addressed by portions of pixel codes during display line trace intervals. The read-outs from these color map memories provide the primary color component signals from which the drive signals for the display monitor kinescope are derived. The pixel codes, from which color map memory addresses are derived, are supplied at video rate to the display processor from the serial output port of dual-ported video random access memory. The color map memories are loaded with new color map data during display retrace intervals. By supplying this new color map data from the serial port of the dual-ported video random-access memory, the color map memories can be rapidly updated.

Abstract: Computer main memory is used for storing relatively densely sampled luminance detail information concerning a television display and for storing relatively sparsely sampled narrowband color-component information concerning the same television display. The relatively densely sampled luminance detail information is read out in substantially real-time from computer main memory during line trace intervals in the television display. The relatively sparsely sampled narrowband color-component information is read out of computer main memory in advanced and compressed time during selected line retrace intervals in the television display.

Abstract: Computer main memory is used for storing relatively densely sampled green and detail information concerning a television display and for storing relatively sparsely sampled red information and blue information concerning the same television display. The relatively densely sampled green and detail information is read out in substantially real-time from computer main memory during line trace intervals in the television display. The relatively sparsely sampled red information and blue information are read out of computer main memory in advanced and compressed time during selected line retrace intervals in the television display.

Abstract: Computer main memory is used for storing relatively densely sampled luminance information concerning a television display and for storing relatively sparsely sampled chrominance information concerning the same television display. The relatively densely sampled luminance information is read out in substantially real-time from computer main memory during line trace intervals in the television display. The relatively sparsely sampled chrominance information is read out of computer main memory in advanced and compressed time during selected line retrace intervals in the television display.

Abstract: Computer main memory is used for storing relatively densely sampled wideband video information concerning a television display and for storing relatively sparsely sampled narrowband video information concerning the same television display. The relatively densely sampled wideband video information is read out in substantially real time from computer main memory during line trace intervals in the television display. The relatively sparsely sampled narrowband video information is read out of computer main memory in advanced and compressed time during selected line retrace intervals in the television display. The wideband video information may be luminance information; and the narrowband video information chrominance information.

Abstract: A number of control signals for accessing a random access memory may be generated using a cascade connection of data latches. A control signal generator produces two non-overlapping timing signals and their complements from a single input clock signal. The non-overlapping signals of each type are connected to alternate ones of the data latches in the cascade chain. The input to the data latch chain receives the memory access pulse which is then used to derive the various control signals for the random access memory. A plurality of flip-flops have their set and reset terminals connected to the output terminals of various ones of the data latches to produce output control signals from each flip-flop. These control signals have the desired timing relationship to the access pulse.

Abstract: A sampled data FIR filter of the type including alternately connected ADDER circuits and delay stages in a serial chain where input samples are multiplied by coefficients and applied in parallel to the ADDER circuits for addition to partial sums therein has respective COUNTER circuits coupled to each ADDER circuit to respond to sum overflows. The COUNTER circuits are serially connected one to another by delay stages. The overflow count corresponding to each signal sample is translated to successive counter in consonance with such partial sum being translated from ADDER circuit to ADDER circuit. The last COUNTER circuit contains the net number of overflows corresponding to the output sum, which overflow signal is indicative of the state of correctness of the output sample.

Abstract: A circuit for incrementing or decrementing a binary number is described. An M bit binary number is applied to M dynamic latch circuits. The latch output signals are applied to M logic units each comprising an exclusive OR, an exclusive NOR and one transistor. The transistors of the respective logic units are connected serially, with the transistor of the logic unit operating on the LSB of the binary number being further connected to a carry in or count signal. The exclusive OR is responsive to the carry in signal and the latched signal to increment/decrement or pass through the respective bit of the binary number. The exclusive NOR is responsive to an Up/Down signal and the latched signal for controlling the conduction state of the respective transistor thereby providing a carry in signal to the input of the next adjacent logic unit operating on the next more significant bit of the binary number.