Patents by Inventor David Latta
David Latta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240076875Abstract: A shingle coating asphalt composition is provided that is produced from a paving grade asphalt. The asphalt composition comprises a paving-grade asphalt that has been modified with one or more polymer additives; and a secondary additive comprising one or more of a viscosity reducing agent, a wax, a salt of a fatty acid ester, and an amide of a fatty acid. The shingle coating asphalt coating composition is used to make a shingle. The shingle includes a substrate, the asphalt, and roofing granules.Type: ApplicationFiled: November 8, 2023Publication date: March 7, 2024Inventors: Carmen Anthony LaTorre, Jacob Paul Honsvick, Christopher Patrick Kasprzak, Daniel James Buckwalter, Edward R. Harrington, Jonathan Ross Davis, Laurand Henry Lewandowski, David Michael Ploense, William Edwin Smith, Scott W. Schweiger, Ganesh Latta
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Publication number: 20240068135Abstract: Interlacing equipment may be used to form fabric and to create a gap in the fabric. The fabric may include one or more conductive strands. An insertion tool may be used to align an electrical component with the conductive strands during interlacing operations. A soldering tool may be used to remove insulation from the conductive strands to expose conductive segments on the conductive strands. The soldering tool may be used to solder the conductive segments to the electrical component. The solder connections may be located in grooves in the electrical component. An encapsulation tool may dispense encapsulation material in the grooves to encapsulate the solder connections. After the electrical component is electrically connected to the conductive strands, the insertion tool may position and release the electrical component in the gap. A component retention tool may temporarily be used to retain the electrical component in the gap as interlacing operations continue.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Inventors: Kyle L. Chatham, Kathryn P. Crews, Didio V. Gomes, Benjamin J. Grena, Storrs T. Hoen, Steven J. Keating, David M. Kindlon, Daniel A. Podhajny, Andrew L. Rosenberg, Daniel D. Sunshine, Lia M. Uesato, Joseph B. Walker, Felix Binder, Bertram Wendisch, Martin Latta, Ulrich Schläpfer, Franck Robin, Michael Baumann, Helen Wächter Fischer
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Patent number: 11913143Abstract: Interlacing equipment may be used to form fabric and to create a gap in the fabric. The fabric may include one or more conductive strands. An insertion tool may be used to align an electrical component with the conductive strands during interlacing operations. A soldering tool may be used to remove insulation from the conductive strands to expose conductive segments on the conductive strands. The soldering tool may be used to solder the conductive segments to the electrical component. The solder connections may be located in grooves in the electrical component. An encapsulation tool may dispense encapsulation material in the grooves to encapsulate the solder connections. After the electrical component is electrically connected to the conductive strands, the insertion tool may position and release the electrical component in the gap. A component retention tool may temporarily be used to retain the electrical component in the gap as interlacing operations continue.Type: GrantFiled: March 4, 2020Date of Patent: February 27, 2024Assignee: Apple Inc.Inventors: Kyle L Chatham, Kathryn P. Crews, Didio V. Gomes, Benjamin J. Grena, Storrs T. Hoen, Steven J. Keating, David M. Kindlon, Daniel A. Podhajny, Andrew L. Rosenberg, Daniel D. Sunshine, Lia M. Uesato, Joseph B. Walker, Felix Binder, Bertram Wendisch, Martin Latta, Ulrich Schläpfer, Franck Robin, Michael Baumann, Helen Wächter Fischer
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Patent number: 9418042Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.Type: GrantFiled: February 10, 2015Date of Patent: August 16, 2016Assignee: Synopsys, Inc.Inventor: David Latta
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Publication number: 20150154143Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.Type: ApplicationFiled: February 10, 2015Publication date: June 4, 2015Inventor: David Latta
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Patent number: 8959269Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.Type: GrantFiled: February 18, 2014Date of Patent: February 17, 2015Assignee: Synopsys, Inc.Inventor: David Latta
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Publication number: 20140281114Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.Type: ApplicationFiled: February 18, 2014Publication date: September 18, 2014Applicant: Synopsys, Inc.Inventor: David Latta
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Patent number: 8688879Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.Type: GrantFiled: June 20, 2008Date of Patent: April 1, 2014Assignee: Synopsys, Inc.Inventor: David Latta
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Publication number: 20090055565Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.Type: ApplicationFiled: June 20, 2008Publication date: February 26, 2009Inventor: David Latta
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Publication number: 20060174081Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.Type: ApplicationFiled: January 14, 2006Publication date: August 3, 2006Inventor: David Latta
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Patent number: 6988154Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.Type: GrantFiled: March 7, 2001Date of Patent: January 17, 2006Assignee: ARC InternationalInventor: David Latta
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Publication number: 20030009612Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.Type: ApplicationFiled: March 7, 2001Publication date: January 9, 2003Inventor: David Latta