Abstract: Methods and apparatuses are provided for accelerating the throughput and or reducing the power consumption of symmetric cryptography algorithms. Certain computations of a symmetric encryption or decryption algorithm are performed during a first phase, the results are saved to memory, and the results are retrieved to encode data during a second phase. If the first phase is implemented while the battery is being charged and the second phase is implemented while the system runs on battery power, the battery life is significantly extended compared to the battery life when all phases are implemented using solely battery power.