Abstract: Techniques, apparatus, and systems for injecting a memory fault can include obtaining first data and second data different from the first data, generating first error detection information based on the first data, writing the second data to a memory unit using a specified address, and using the first error detection information as error detection information for the second data to create a memory fault condition.

Abstract: An interrupt controller for a disk controller includes an interrupt scanner module that receives a plurality of interrupt requests (IRQs) from a plurality of corresponding interrupt sources, performs a scan of respective vector values of the plurality of IRQs, and selectively outputs a priority based on the scan. An interrupt generation module receives the priority and generates at least one of a fast interrupt and a regular interrupt based on the priority.

Abstract: An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers without conflicts. The processors operate at different frequencies, while the servo-controller and the servo controller interface operate in same or different frequency domains. The pipeline control module resolves conflict between the first and second processor transaction. The speed matching module ensures communication without inserting wait states in a servo controller interface clock domain for write access to the servo controller and there is no read conflicts between the first and second processor. The controller also includes a hardware mechanism for indivisible register acess to the first or second processor. The hardware mechanisim includes a hard semaphore and/or soft semaphore.

Abstract: A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is pending; comparing the received vector value with a vector value of the pending interrupt; and replacing a previous vector value with the received vector value if the received vector value has higher priority. The system includes, at least one register for storing a trigger mode value which specifies whether an interrupt is edge triggered or level sensitive, and a vector address field that specifies a priority and address for an interrupt, and a mask value which masks an interrupt source. Also provided is a method for generating a fast interrupt. The method includes, receiving an input signal from a fast interrupt source; and generating a fast interrupt signal based on priority and a mask signal.

Abstract: A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

Abstract: A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

Abstract: A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is pending; comparing the received vector value with a vector value of the pending interrupt; and replacing a previous vector value with the received vector value if the received vector value has higher priority. The system includes, at least one register for storing a trigger mode value which specifies whether an interrupt is edge triggered or level sensitive, and a vector address field that specifies a priority and address for an interrupt, and a mask value which masks an interrupt source. Also provided is a method for generating a fast interrupt. The method includes, receiving an input signal from a fast interrupt source; and generating a fast interrupt signal based on priority and a mask signal.

Abstract: An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers without conflicts. The processors operate at different frequencies, while the servo-controller and the servo controller interface operate in same or different frequency domains. The pipeline control module resolves conflict between the first and second processor transaction. The speed matching module ensures communication without inserting wait states in a servo controller interface clock domain for write access to the servo controller and there is no read conflicts between the first and second processor. The controller also includes a hardware mechanism for indivisible register access to the first or second processor. The hardware mechanism includes a hard semaphore and/or soft semaphore.

Abstract: A method and apparatus for setting a priority sequence among a plurality of requesters using a common destination within a computer system. An advantage is that all requesters contending for the common destination will have timely access with respect to all other competing requesters. In a first exemplary embodiment of the present invention, a priority controller can use a two-level priority scheme to select the next requester. The first level of priority alternates between an external requester and an on-card requester where every other set of data is from the external requester. The second level of priority alternates between on-card modules during an on-card priority cycle. In an alternative exemplary embodiment, the priority controller can stack a request to transfer acknowledge and data information from an external requester if it is busy. The priority controller also prevents sending an acknowledgment/data cycle out to an external source to prevent sending more data than the FIFO stacks can accommodate.

Abstract: An apparatus and method for transferring data sets between a storage controller and a number of daisy chained main memories on separate circuit elements at high speed. Each main memory has coupled control logic which receives a data set from the storage controller, latches and retransmits the data set to the next main control logic and coupled memory, which next control logic repeats the process, and which can be continued through a number of coupled control logic units and main memories. A data set includes a header with an address range and function information. If data is to be sent from the storage controller it is appended to the header. Each storage controller compares the address range with the address range of the coupled memory, and if within the address range and for a write, will store the appended data in the header address in the coupled memory.

Abstract: A method and apparatus for removing soft errors in a memory element by providing dedicated hardware associated with each memory element which monitors for soft errors as data is read from the memory element. Further, when a soft error is detected, the dedicated hardware may correct the soft error and may further initiate a write operation and over-write the corrupted data word with a corrected data word. This may be accomplished without any intervention by the system.

Abstract: An apparatus for and method of detecting errors in a system which employs multi-bit wide memory elements. The error correction code (ECC) of the present invention is odd weighted and thus has an odd number of check bits. Further, the exemplary ECC has a single code in each of the check bit columns. The error correction code of the present invention may detect byte errors thereby providing a mechanism for detecting errors within system which employs multiple bit wide memory elements. The data word in an exemplary embodiment may comprise 44 bits including 36 data bits, one IF bit, and seven check bits. The 44 bit data word may comprise eleven (11) four bit bytes wherein each of the eleven (11) four bit bytes of the 44 bit data word are stored in a different memory element. Each of the 44 bits of the data word are stored in an appropriate one of the eleven (11) memory elements to maximize the error detection capability of the exemplary error correction code.

Abstract: A method of and apparatus for continuously checking a CMOS SRAM memory system. Each memory cell has a bistable circuit for retaining the state of the cell, along with a totally redundant bistable circuit. Added circuitry provides continuous comparing of the binary state of the bistable circuit and the redundant bistable circuit within the memory cell. This testing is performed at a low level within the memory cell eliminating the power dissipation and size requirements associated with additional drivers. An error line is shared amongst a number of memory cells. By continuously monitoring in this manner, the time of failure as well as the fact of failure can be determined.

Abstract: A method of and apparatus for continuous parity checking within a CMOS SRAM memory system. Each cell has added circuitry which permits continuous reading of the binary state of the cell. The states of each cell are combined to produce a parity determination for a given data array. By continuously monitoring parity in this manner, the time of failure as well as the fact of failure can be determined.

Abstract: A novel unconditional clock and automatic refresh logic system is provided which comprises a source of unconditional clock pulses coupled to the memory control logic in a manner which permits automatic refreshing of a dynamic memory. There is further provided clock logic means which sense the conditions in the dynamic memory system during which the dynamic memory is not being refreshed. There is further provided, means for generating automatic clock refresh signals coupled to the memory control logic for initiating continuous automatic refresh cycles when the system clock is being shutdown.

Abstract: An error correcting check of a memory system is provided when a memory in which the Dynamic Random Access Memory (DRAM) is of the type which has input lines that are directly coupled to its output lines. Utilizing this type of DRAM, the memory system employs controls, input, output and read circuitry to read bits out of the memory via the output circuitry and write circuitry to write bits into the memory via the input circuitry. An error checking and correction circuit is coupled to the output means which includes a check bit generator and a syndrome generator, and a control means energizes the error checking and correcting means during the write cycle, as well as the read cycle, so that the errors are detected during the write cycle as well as the read cycle. In this manner, errors which occur in circuitry other than the memory, which includes the memory driving and reading logic and also the check bit generator logic translators and syndrome generators, may be separately detected from memory errors.

Abstract: A multibank computer memory system is provided in which the storage banks monitor the initiate line while each bank operation is being processed to verify that another initiate is not received before it can be processed. This serves to check that the control logic is not in error, and that there is no error between the control section and the banks.