Abstract: A time delay circuit that produces a constant delay and is independent of supply voltage. The time delay circuit has a current mirror circuit, a voltage shift circuit, an inverter and a capacitor. The inverter will trip at a predetermined voltage level. A capacitor is coupled to the current mirror circuit and to the inverter for generating a portion of the delay time. A voltage shift circuit is coupled to the inverter for approximately mirroring a voltage shift in the current mirror circuit thereby allowing the time delay circuit to be voltage independent.

Abstract: A precision oscillator circuit having a wide adjustable operating frequency range and an adjustable duty cycle. The precision oscillator use a window comparator circuit for monitoring a voltage of a capacitive element. The window comparator circuit has a first operating voltage edge and a second operating voltage edge wherein the first operating voltage edge latches an output signal of the window comparator circuit at one level when the voltage of the capacitive element is greater than the first operating voltage edge. The second operating voltage edge brings the output signal of the window comparator circuit back to an initial level when the voltage of the capacitive element is greater than the second operating voltage edge. A precision current reference source is coupled to the capacitive element and to the window comparator circuit. The precision current reference is used for generating currents which are insensitive to temperature, supply voltage, and process variations.

Abstract: A precision bandgap reference circuit which uses an operational amplifier that has the positive and negative input terminals connected to a diode/resistor combination and a diode respectively. The output of the operational amplifier drives a diode connected PMOS transistor which regulates current sources which drives into the diode/resistor combination and the diode inputs to the operational amplifier. This allows the operational amplifier to have enough gain to minimize errors across the diode/resistor combination and the diode inputs to the operational amplifier. This also allows an output stage driven by the operational amplifier to be biased with a Proportional To Absolute Temperature (PTAT) current which is well controlled.

Abstract: A zero-current start-up circuit for a reference circuit which is initially unbiased and which has internal nodes that needs to be regulated to a predetermined voltage. When the start-up circuit is enabled, a switching transistor is turned on which enables the reference circuit to generate an internal reference current which regulates an output current to a predetermined value set by the reference circuit. The output current flows through a voltage drop device and when the voltage level reaches a predetermined value, the start-up circuit is disabled eliminating the current path.

Abstract: A modification circuit (30) is thermally coupled to and electrically isolated from a circuit element (20) of a utilization circuit (10). During modification, current pulses are passed through an isolation circuit (40) to the modification circuit which heats the circuit element, e.g., a resistor, of the utilization circuit substantially above the normal operating temperature range of the element, thereby modifying the electrical characteristics of the resistor and therefore those of the utilization circuit to which it is connected. During normal operation of the utilization circuit the circuit element of the utilization circuit is electrically isolated from the modification circuit.

Abstract: A current limit circuit (10) uses a reference current (28) with zero temperature coefficient. A feedback loop (18, 26, 22) maintains substantially equal V.sub.GS for first (22) and second (24) transistors. The reference current sets the current through the first transistor which therefore limits the current in the second transistor. The second transistor is a power device that supplies current to a squib detonation device (38) in automotive air bag application.

Abstract: A power off-loading circuit (10) includes an IC device (11) and a discrete resistor (21), which provide a regulated voltage at an output pin (19) of the IC device (11). The IC device (11) includes a first FET (12), a second FET (14), and an operational amplifier (16). For a low voltage at an input pin (13) of the IC device (11), the first FET (12) conducts a current to a load (25) connected to the output pin (19). For a high voltage at the input pin (13), a large portion of the current is directed through the discrete resistor (21) and the second FET (14). A large portion of power is off-loaded from the IC device (11) and dissipated in the discrete resistor (21) thereby permitting the use of surface mount techniques.

Abstract: A lateral transistor (14) is configured as a reverse protection diode that allows low and high current modes of operation while maintaining low forward voltage drop. The base region (38) of the lateral transistor is formed inside a collector ring (34) and adjacent to the emitter region (36). In low current mode, the transistor operates as a conventional diode. In high current mode, the excessive number of minority carriers injected into the base region causes the device to enter conductivity modulation that effectively increases the doping concentration and lowers the bulk resistance. The lower bulk resistance keeps the forward voltage drop low. By having the base region inside the collector ring, the bulk resistance is kept low to aid in the onset of conductivity modulation. Thus, the transition between low current mode and high current mode is minimized.

Abstract: A data transmitter (12) on a data bus (16) keeps its drive transistor (36) at a minimum bias according to the minimum voltage level on the data bus. The current flowing through the drive transistor in response to a data signal, or a proportional current, is mirrored (52, 54) and compared to a current source (60). Any mismatched between the mirrored current and the current source enables a transistor (58) to bias the drive transistor so that it maintains a minimum conduction state. The base of the drive transistor is held one V.sub.be above the minimum voltage on the data bus. The minimum bias on the base of the drive transistor keeps it conducting so that the transition to full conduction is smooth and prevents any sharp transitions that may cause undesired radiated emissions.

Abstract: A resistance measuring circuit (10) generates a predetermined reference voltage and impresses that reference voltage across a squib detonation device (12). The resulting current flowing through the squib is mirrored by a current mirror (42,52,54) for providing multiple mirrored currents. The mirrored currents are compared to known current sources (58,60). The output signals go high or low depending on whether the mirrored currents are greater than or less than the fixed current sources. The output signals provide an indication as to whether the measured squib resistance is within a specified resistance range. The current sources may be precisely matched to maintain high accuracy in measuring the resistance.

Abstract: A subscriber line interface circuit (SLIC) sets AC and DC output impedances as seen by first and second transmission signals. The common mode variation and differential variation of the first and second transmission signals is AC-sensed to provide a common mode feedback signal and a differential feedback signal which in turn controls the AC output impedance. The DC component of the first and second transmission signals is blocked allowing downstream amplifiers to operate at reduced power supply potentials. The DC variation of the first and second transmission signals is also sensed for providing a DC feedback signal to control the DC output impedance.

Abstract: A compandor circuit uses a DC-coupled compressor to reduce the required IC package size to 8-pins. A delta gain stage and rectifier in the feedback path of the compressor circuit receive the AC and DC components of the compressed analog output signal Features of the delta gain stage and rectifier eliminate the need for any AC-coupling capacitors in the feedback path thereby reducing the number of external components The remaining external components may be made smaller and manufactured as surface mount devices An expandor circuit receives a second compressed analog signal and expands it to full amplitude dynamic range.

Abstract: A transient protection circuit provides protection from high voltage transients appearing along a transmission line by sensing a predetermined threshold of the voltage developed thereon and opening the conduction path through first and second switching circuits in the transmission line. The switching circuits are implemented with first and second serially coupled transistors sharing a common drain and enabled by a control signal during normal operation. The first and second transistors each have a diode oriented to conduct from the source to the drain for bi-directional operation. During high voltage transient conditions, a sensing circuit detect a predetermined threshold of the potential on the transmission line and disables one of the first and second transistors which opens the conduction path through the first and second switching circuits thereby suppressing the surge currents flowing therethrough.

Abstract: A telephone line card circuit includes an operational amplifier circuit having first and second inputs and an output. A field-effect transistor circuit has first, second and control electrodes, the control electrode is coupled to the output of the operational amplifier circuit, the first electrode is coupled to the TIP/RING terminal, and the second electrode is coupled to the second input of the operational amplifier circuit. A first resistor is coupled between the TIP/RING terminal and the first input of the operational amplifier circuit. A second resistor is coupled between the first input of the operational amplifier circuit and a terminal of the circuit whereby the terminal of the circuit is typically coupled to a supply voltage terminal.

Abstract: A mute circuit for an audio amplifier has been provided. The mute circuit alternately switches from a normal mode of operation to a mute mode of operation. In the normal mode of operation, the mute circuit utilizes a first op amp circuit to amplify an input signal by a predetermined factor. In the mute mode of operation, the mute circuit utilizes a second op amp circuit which is configured as an unity gain amplifier. In the mute mode, DC shifts occurring at the output of the second op amp circuit are minimized. Further, the second op amp circuit has a low output impedance thereby providing excellent attenuation of an audio input signal when the mute circuit is utilized in an audio amplifier application.

Abstract: A full wave rectifier/averaging circuit for processing an input signal having a large dynamic range. A rectification circuit is responsive to the input signal for providing a first signal to a current mirror whereby the current mirror provides a second signal in response to the first signal. An averaging circuit is coupled to the current mirror to perform averaging of the second signal. An output circuit is coupled to the averaging circuit to provide an output signal at an output terminal.

Abstract: An amplifier output stage with minimum circuitry and optimum performance for providing a SAT-to-SAT output voltage signal at an output terminal. The amplifier output stage includes a first transistor having a collector coupled to the output terminal for sourcing current thereto, a base coupled to a first supply voltage terminal, and an emitter coupled to the first supply voltage terminal. A second transistor having a collector coupled to the output terminal for sinking current thereat, a base, and an emitter coupled to a second supply voltage terminal. A third transistor having a collector, a base coupled to the base of the second transistor, and an emitter coupled to the second supply voltage terminal by a first resistor. A fourth transistor having a collector coupled to the first supply voltage terminal, a base coupled to an input terminal, and an emitter coupled to the base of the third transistor.

Abstract: In an output stage of an operational amplifier comprising first and second NPN output transistors a circuit is coupled between the positive supply conductor and the collector of the first NPN transistor for providing a boosted base current drive thereto as a function of the load current sourced from the emitter of the first transistor to the output of the operational amplifier. The circuit senses the collector current flowing through the first transistor for increasing the base current drive thereto as the collector current increases.

Abstract: An operational amplifier includes a first and second input JFETs having gate electrodes which are coupled to first and second input terminals respectively. A single ended output is taken from the drain of one of the JFETs and applied to an output gain stage including a Miller compensation capacitor. Circuitry is provided for producing a low impedance at the drain of the second JFET at high operating frequencies. This circuitry comprises an NPN transistor having an emitter coupled to ground, a base coupled to the drain of the first JFET, and a collector coupled via a resistor to the common sources of the input JFETs. A capacitor is coupled between the collector of the NPN transistor and the drain of the first JFET.

Abstract: A JFET circuit generates an adjustable current having a temperature coefficient proportional to I.sub.DSS where I.sub.DSS is the drain current of a JFET when its source and gate are shorted. The JFET has a source terminal coupled to a source of supply voltage. An adjustable resistor is coupled between the gate and source terminals of the JFET. A reference current is supplied to the resistor, which reference current is proportional to the JFET's pinch-off voltage. The desired current appears at the drain of the JFET.