Abstract: A commutation controller for a switched reluctance machine has separate timer circuits for determining the firing signals for motoring and generating modes. Each timer circuit comprises a ramp generator and a pair of comparators which denote the ON- and OFF-angle as the ramp output passes preset thresholds applied to the comparators. A multiplexer selects the output from one of the motoring and generating timers according to the mode of machine operation. By producing timing signals for the motoring and generating modes separately and continuously, a transition between motoring and generating modes can be carried out smoothly without timing error.

Abstract: A demodulator for a pulse width modulated signal comprises a counter arranged to count in one direction when the PWM signal is "high" and in the opposite direction when the PWM signal is "low" to arrive at a count representative of a duty cycle. As a result, a value representative of the duty ratio of the PWM signal can be obtained from the up/down counter. In a further embodiment, the up/down counter is clocked by the output of a frequency multiplier, the output of the frequency multiplier having a frequency determined by the pulse width modulated signal frequency multiplied by a predetermined factor. The value of the duty ratio of the PWM signal can then be found regardless of the frequency of the PWM signal.

Abstract: An electric machine includes a rotor and a stator, a rotor position transducer being provided to detect the position of the rotor relative to the stator. Phase windings are sequentially energizable to drive the rotor. The rotor position transducer is powered by the energization of one or more windings thus removing the need for an additional power supply for the rotor position transducer.

Abstract: A method of memory matrix interpolation in an ASIC processor requires a reduced amount of program code and memory space in the interpolation routine by shifting values in the interpolation routine between shift registers and overwriting redundant data in the shift registers with intermediate results. A switched reluctance drive system incorporating such a method provides similar advantages.

Abstract: An analog to digital converter includes a comparator, an up/down counter and a pulse width modulator. The analog input to the comparator initially causes the counter to count up. The counter output is the converted digital word. The word is used to vary the modulation duty cycle of the modulator output which is compared with the analog input to the comparator. When the modulator output exceeds the analog input, the comparator output changes and the counter counts down, maintaining a digital output from the counter at the value of the converted analog signal.

Abstract: A failure detector for a position encoder which uses a plurality of position sensors. The failure detector receives position signals from the plurality of position sensors. The position signals represent the rotor position for a switched reluctance machine, and the position signals have allowable states and allowable output state sequences that occur if the position encoder is operating properly. If one or more of the plurality of sensors fail or the rotating element of the position encoder is damaged, an illegal state occurs in the position signals from the position sensors. The failure detector produces a failure signal upon the occurrence of an illegal state. In addition, the failure detector monitors the sequence of the output states and generates a failure when the output states change in a sequence that is not one of the allowed sequences. The machine controller can respond to the failure signal to stop machine operation or trigger an alternate positioning scheme.

Abstract: The present invention employs digital circuitry to compensate for variations in DC link voltage transmitted to a switched reluctance machine. The digital voltage compensation system of the present invention periodically samples the DC link voltage and actual rotor speed, then supplies the samples in digital form to a microcontroller that derives a compensated speed signal to compensate for changes in DC link voltage.

Abstract: A circuit and method for controlling a switched reluctance drive having at least one phase winding and a rotor position encoder that provides a set of signals corresponding to the absolute position of the rotor relative to the stator. The circuit monitors the set of signals and generates a high frequency clock signal having a frequency substantially proportional to the frequency at which the set of signals changes state. The high frequency clock signal comprises a number of digital pulses for each rotor revolution that is an integral multiple of the number of digital pulses from the rotor position transducer for each rotor revolution and corresponds to the incremental position of the rotor. The high frequency clock signal is applied to a counter that is reset upon each change in state of the set of signals. The output of the counter is compared to predetermined values and the at least one phase winding is energized and de-energized in response to the results of the comparison.

Abstract: A sensor failure detection circuit for a position encoder, the sensor failure detection circuit receiving from a first set of at least one position sensor position signals which change state at a high resolution and from a second set of at least one position sensor position signals which change state at a lower resolution, the detection circuit monitoring a count for the position signals at the high resolution between states of the position signals at the lower resolution and comparing the count with a predetermined range which represents an expected count for the position signals at the high resolution between the states of the position signals at the lower resolution.