Abstract: A fluid dispensing apparatus may be provided that includes a fluid reservoir configured to hold a liquid fluid. The fluid dispensing apparatus may include fluid output zones with at least one of the fluid output zones including plural fluid pumps. Each of the fluid pumps may have a flow rate at which the liquid fluid is pumped by the fluid pump. A slot die may also be provided that has a slot for each of the fluid output zones. The fluid dispensing apparatus may also include a relief valve mechanically connected to each of the fluid pumps, and a control device. The control device may be functionally connected to each relief valve, and the control device may be adapted to selectively instruct each valve to open or close to produce differing volume rates of fluid through each slot based on the relief valves selected.

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.

Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to execute a sequence of scrubbing transactions on the first memory and execute a functional transaction on the second memory. One of the scrubbing transactions and the functional transaction are executed concurrently.

Abstract: A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.

Abstract: Compounds, and pharmaceutically acceptable salts thereof, useful as inhibitors of sodium channels are provided. Also provided are pharmaceutical compositions comprising the compounds or pharmaceutically acceptable salts and methods of using the compounds, pharmaceutically acceptable salts, and pharmaceutical compositions in the treatment of various disorders, including pain.

Abstract: A vacuum sealer includes: a housing comprising a vacuum chamber therein; a vacuum pump in fluid communication with the vacuum chamber; a sealing mechanism adjacent a periphery of the vacuum chamber; a valve positioned and configured to releasably seal the vacuum chamber, the valve movable between a first position, in which the valve forms a seal with the sealing chamber, and a second position, in which the valve does not form a seal with the sealing chamber; and a controller operatively connected with the vacuum pump, the sealing mechanism, and the valve. The controller is configured to move the valve from the first position to the second position during sealing.

Abstract: A printing plate pressure adjustment system for a can decorator including a printing plate cylinder assembly having a printing plate cylinder drive shaft, and a blanket wheel. The system, includes an actuator, a control system structured to control operation of the actuator to adjust a pressure, between the printing plate cylinder assembly and the blanket wheel, an eccentric bushing disposed around the printing plate cylinder drive shaft, wherein rotation of the eccentric bushing causes the printing plate cylinder to move toward or away from the blanket wheel, and a drive mechanism coupled between the actuator and the eccentric bushing, wherein operation of the actuator causes the drive mechanism to rotate the eccentric bushing.

Abstract: Exemplary embodiments of a kamado-style cooker pizza oven conversion device are disclosed. Certain embodiments detachably mount within a kamado-styled cooker such that the lid of the cooker rests at an angle on the top of the device and thereby “closes off” and defines a cooking space within the interior that takes advantage of the pizza oven-like features of a kamado cooker. With an embodiment of the solution installed in a kamado cooker, an open doorway or window is defined for allowing a user to insert a pizza into the cooking space and place the pizza on a pizza stone held by the device. Embodiments allow for cooking to occur simultaneously via conductive, convective and radiant thermal energy transfer.

Abstract: The present invention relates to compounds that act as DUX4 repressors, suitable for the treatment of diseases related to DUX4 expression, such as muscular dystrophies. It also relates to use of such compounds, or to methods of use of such compounds.

Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions.

Abstract: The present invention relates to cyclic cyanoenone derivatives of Formula (I) or pharmaceutically acceptable salts or solvates thereof, wherein R1, R2, R3, R4 and m are as defined herein. The present invention also relates to pharmaceutical compositions comprising the cyclic cyanoenone derivatives of Formula (I) and to their use in therapy.

Abstract: The present disclosure relates to an additive manufacturing system for forming at least one of forming a part or modifying a surface using a volume of polymerizable resin. The system makes use of a subsystem for generating power output signals, and at least one acoustic transducer. The acoustic transducer is placed in a vicinity of the volume of polymerizable resin and is responsive to the power output signals. The acoustic transducer generates and projects ultrasound energy in response to receiving the power output signals to at least one spatial location within the volume of resin to cause polymerization of at least a portion of the volume of resin to at least one of form the part or modify the surface.

Abstract: Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from a master directory and/or from error correcting code (ECC) bits of the physical address. Based on the CI, the CMC determines a number of memory blocks to be read for the memory read request, and reads the determined number of memory blocks. In some aspects, a CMC is configured to receive a memory write request to a physical address in the system memory, and generate a CI for write data based on a compression pattern of the write data. The CMC updates the master directory and/or the ECC bits of the physical address with the generated CI.

Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

Abstract: Systems and techniques for modifying a subsection of uploaded media are presented. An instruction component receives a media file and a media enhancement instruction that includes enhancement data and media interval data for a first segment of the media file. A processing component modifies the first segment of the media file associated with the media interval data based on the enhancement data to generate an edited first segment of the media file. A finalization component generates an edited version of the media file that includes the edited first segment of the media file and at least a second segment of the media file that is not modified based on the enhancement data.

Abstract: The invention provides antibodies and antigen-binding fragments thereof that selectively bind to an epitope within the core region of transglutaminase type 2 (TG2). Novel epitopes within the TG2 core are provided. The invention provides human TG2 inhibitory antibodies and uses thereof, particularly in medicine, for example in the treatment and/or diagnosis of conditions including Celiac disease, scarring, fibrosis-related diseases, neurodegenerative/neurological diseases and cancer.

Abstract: In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The CPU is arranged to execute program instructions to manipulate data in at least a first or second secure context. Each of the first and second caches stores a secure code for indicating the at least first or second secure contexts by which data for a respective cache line is received. The first and second level caches maintain coherency in response to comparing the secure codes of respective lines of cache and executing a cache coherency operation in response.