Abstract: The semiconductor device includes: a gate electrode on a semiconductor substrate via a gate insulating film; an offset drain layer in the semiconductor substrate on one side of the gate electrode; a drain layer on the offset drain layer; and a source layer in the semiconductor substrate on another side of the gate electrode. The semiconductor device further includes: a protective film covering the semiconductor substrate; a field plate on the protective film, and having a portion above the offset drain layer; and a field plug connected to the field plate and in the protective film and above the offset drain layer, in such a manner as to avoid reaching the offset drain layer.

Abstract: A LDMOS transistor that may include (i) a first region that is a reduced surface field (RESURF) implant region of a first type; (ii) a second region that is a RESURF implant region of a second type, wherein the first type differs from the second type; (iii) a gate; (iv) a stepped oxide region and a gate oxide region that are positioned above the first region and below the gate.

Abstract: A LDMOS transistor that may include (i) a first region that is a reduced surface field (RESURF) implant region of a first type; (ii) a second region that is a RESURF implant region of a second type, wherein the first type differs from the second type; (iii) a gate; (iv) a stepped oxide region and a gate oxide region that are positioned above the first region and below the gate.

Abstract: Some demonstrative embodiments include a Metal-Oxide-Semiconductor (MOS) transistor including a multi-split gate. For example, an Integrated Circuit (IC) may include at least one MOS transistor, the MOS transistor may include a source; a drain; a body; and a multi-split gate including a control gate component configured to control conductivity of the MOS transistor, and at least first and second field plate gate components, the first field plate gate component is electrically isolated from the second field plate gate component, the first and second field plate gate components are electrically isolated from the control gate.

Abstract: Some demonstrative embodiments include a Metal-Oxide-Semiconductor (MOS) transistor including a multi-split gate. For example, an Integrated Circuit (IC) may include at least one MOS transistor, the MOS transistor may include a source; a drain; a body; and a multi-split gate including a control gate component configured to control conductivity of the MOS transistor, and at least first and second field plate gate components, the first field plate gate component is electrically isolated from the second field plate gate component, the first and second field plate gate components are electrically isolated from the control gate.

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device that may include an oxide region that comprises a bottom surface; a drain that is positioned between a left drift region and a right drift region and below the bottom surface; wherein the oxide region further comprises a first sloped surface and a second sloped surface; wherein a first angle between the first sloped surface and the bottom surface does not exceed twenty degrees; and wherein a second angle between the second sloped surface and the bottom surface of the oxide region does not exceed twenty degrees.

Abstract: According to an embodiment of the invention there may be provided a die that may include (a) a first region of a first type; (b) a first conductor that contacts the first region; (c) a substrate having a substrate portion of the first type; wherein the substrate portion contacts the first region; an intermediate region of a second type; wherein the first type and the second type are selected from an n-type semiconductor and a p-type semiconductor; wherein the first type differs from the second type; (d) a second region of the second type; (e) a second conductor that contacts the second region; (f) a third region of the second type; (g) a third conductor that contacts the third region; (h) a fourth region of the first type; wherein the third region contacts the fourth region and does not contact the intermediate region; (i) a fourth conductor that contacts the intermediate region to form a first Schottky diode.

Abstract: According to an embodiment of the invention there may be provided a die that may include (a) a first region of a first type; (b) a first conductor that contacts the first region; (c) a substrate having a substrate portion of the first type; wherein the substrate portion contacts the first region; an intermediate region of a second type; wherein the first type and the second type are selected from an n-type semiconductor and a p-type semiconductor; wherein the first type differs from the second type; (d) a second region of the second type; (e) a second conductor that contacts the second region; (f) a third region of the second type; (g) a third conductor that contacts the third region; (h) a fourth region of the first type; wherein the third region contacts the fourth region and does not contact the intermediate region; (i) a fourth conductor that contacts the intermediate region to form a first Schottky diode.

Abstract: The application relates to methods for producing a polycarbonate resin having a narrowed molecular weight distribution, specifically, the application relates to the use of a redistribution catalyst and a feedback loop control mechanism to prepare narrow molecular weight distribution resin.