Abstract: A silica aerogel having a mean pore size less than 5 nm with a standard deviation of 3 nm. The silica aerogel may have greater than 95% solar-weighted transmittance at a thickness of 8 mm for wavelengths in the range of 250 nm to 2500 nm, and a 400° C. black-body weighted specific extinction coefficient of greater than 8 m2/kg for wavelengths of 1.5 ?m to 15 ?m. Silica aerogel synthesis methods are described. A solar thermal aerogel receiver (STAR) may include an opaque frame defining an opening, an aerogel layer disposed in the opaque frame, with at least a portion of the aerogel layer being proximate the opening, and a heat transfer fluid pipe in thermal contact with and proximate the aerogel layer. A concentrating solar energy system may include a STAR and at least one reflector to direct sunlight to an opening in the STAR.

Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer.

Abstract: A two step process is disclosed for forming a silicon oxide layer over a stepped surface of a semiconductor wafer while inhibiting the formation of voids in the oxide layer which comprises depositing a layer of an oxide of silicon over a stepped surface of a semiconductor wafer in a CVD chamber by flowing into the chamber a gaseous mixture comprising a source of oxygen, a portion of which comprises O.sub.3, and tetraethylorthosilicate as the gaseous source of silicon while maintaining the pressure in the CVD chamber within a range of from about 250 Torr to about 760 Torr and then depositing a second layer of oxide over the first layer in a CVD chamber by flowing into the chamber a gaseous mixture comprising a source of oxygen, a portion of which comprises O.sub.3 ; and tetraethylorthosilicate as the gaseous source of silicon while maintaining the CVD chamber at a lower pressure than during the first deposition step.

Abstract: An integrated modular multiple chamber vacuum processing system is disclosed. The system includes a load lock, may include an external cassette elevator, and an internal load lock wafer elevator, and also includes stations about the periphery of the load lock for connecting one, two or several vacuum process chambers to the load lock chamber. A robot is mounted within the load lock and utilizes a concentric shaft drive system connected to an end effector via a dual four-bar link mechanism for imparting selected R-.theta. movement to the blade to load and unload wafers at the external elevator, internal elevator and individual process chambers. The system is uniquely adapted for enabling various types of IC processing including etch, deposition, sputtering and rapid thermal annealing chambers, thereby providing the opportunity for multiple step, sequential processing using different processes.

Abstract: A planarizing process is disclosed for planarizing an integrated circuit structure using a low melting inorganic planarizing material which comprises flowing while depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer if insulating material such as an oxide of silicon and then dry etching the low melting inorganic planarizing layer to planarize the structure. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are carried out without removing the integrated circuit structure from the vacuum apparatus. An additional etching step may be carried out after depositing the insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.

Abstract: Gas chemistry and a related RIE mode process is described for etching silicides of the refractory metals titanium, tantalum, tungsten and aluminum and for etching composites of these silicides on polycrystalline silicon layers. BCl.sub.3 is added to the HCl/Cl.sub.2 gas chemistry used for the polysilicon etch along with additives selected from fluorinated gases and oxygen to satisfy the multiple requirement of the two-step silicide-polysilicon etch process, including the silicide-to-polysilicon etch ratio requirement.

Abstract: A magnetic field enhanced single wafer plasma etch reactor is disclosed. The features of the reactor include an electrically-controlled stepped magnetic field for providing high rate uniform etching at high pressures; temperature controlled reactor surfaces including heated anode surfaces (walls and gas manifold) and a cooled wafer supporting cathode; and a unitary wafer exchange mechanism comprising wafer lift pins which extend through the pedestal and a wafer clamp ring. The lift pins and clamp ring are moved vertically by a one-axis lift mechanism to accept the wafer from a cooperating external robot blade, clamp the wafer to the pedestal and return the wafer to the blade. The electrode cooling combines water cooling for the body of the electrode and a thermal conductivity-enhancing gas parallel-bowed interface between the wafer and electrode for keeping the wafer surface cooled despite the high power densities applied to the electrode.

Abstract: An apparatus is disclosed for removing one or more materials deposited on the backside and end edges of a semiconductor wafer which includes means for urging the front side of the wafer against a faceplate in a vacuum chamber; means for flowing one or more gases through a space maintained between the front side of the wafer and the faceplate; and means for forming a plasma in a gap maintained between the backside of the wafer and susceptor to remove materials deposited on the backside and end edge of the wafer; the gas flowing through the space between the front side of the wafer and the faceplate acting to prevent the plasma from removing materials on the front side of the wafer.

Abstract: A planarizing process for planarizing an integrated circuit structure in a CVD apparatus is disclosed using a low melting inorganic planarizing material which comprises flowing white depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon, then dry etching the low melting inorganic planarizing layer to planarize the structure, and then depositing a further layer of an insulating material to encapsulate any remaining portions of the low melting glass planarizing layer which may be hygroscopic. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are all carried out without removing the integrated circuit structure from the apparatus.

Abstract: Gas chemistry and a related RIE mode process is described for etching silicides of the refractory metals titanium, tantalum, tungsten and aluminum and for etching composites of these silicides on polycrystalline silicon layers. BCl.sub.3 is added to the HCl/Cl.sub.2 gas chemistry used for the polysilicon etch along with additives selected from fluorinated gases and oxygen to satisfy the multiple requirement of the two-step silicide-polysilicon etch process, including the silicide-to-polysilicon etch ratio requirement.

Abstract: A planarizing process is disclosed for planarizing an integrated circuit structure using a low melting inorganic planarizing material which comprises flowing while depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon and then dry etching the low melting inorganic planarizing layer to planarize the structure. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are carried out without removing the integrated circuit structure from the vacuum apparatus. An additional etching step may be carried out after depositing the insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.

Abstract: A method and apparatus are disclosed for removing one or more materials deposited on the backside and end edges of a semiconductor wafer which comprises urging the front side of the wafer against a faceplate in a vacuum chamber; flowing one or more gases through a space maintained between the front side of the wafer and the faceplate; and forming a plasma in a gap maintained between the backside of the wafer and susceptor to remove materials deposited on the backside and end edge of the wafer; the gas flowing through the space between the front side of the wafer and the faceplate acting to prevent the plasma from removing materials on the front side of the wafer.

Abstract: An improved process for the selective deposition of tungsten on a masked semiconductor wafer is disclosed which comprises cleaning the surfaces of the wafer in an air-tight cleaning chamber, then transferring the cleaned wafer to a vacuum deposition chamber such as a CVD chamber for selective deposition of tungsten thereon without exposing the cleaned wafer to conditions which would recontaminate the cleaned wafer prior to said deposition, and then selectively depositing tungsten on the unmasked surfaces of the cleaned wafer.

Abstract: An improved process is disclosed for the deposition of a layer of tungsten on a semiconductor wafer in a vacuum chamber wherein the improvements comprise depositing tungsten on the semiconductor wafer in the presence of nitrogen gas to improve the reflectivity of the surface of the resulting layer of tungsten; maintaining the vacuum chamber at a pressure of from about 20 to 760 Torr to improve the deposition rate of the tungsten, as well as to improve the reflectivity of the tungsten surface; and, when needed, the additional step of forming a nucleation layer on the semiconductor layer prior to the step of depositing tungsten on the semiconductor wafer to improve the uniformity of the deposited tungsten layer.

Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer.

Abstract: An improved planarization process is disclosed which comprises depositing over a patterned integrated circuit structure on a semiconductor wafer a conformal insulation layer by ECR plasma deposition of an insulation material. The ECR plasma deposition is carried out until the trenches or low regions between adjacent raised portions of the structure are completely filled with insulation material. A planarization layer of a low melting glass material, such as a boron oxide glass, is then flowed as it is deposited over the integrated circuit structure to a depth or thickness sufficient to cover the highest portions of the ECR plasma deposited insulation layer. This planarization layer is then anistropically etched back sufficiently to provide a planarized surface on the ECR plasma deposited insulation layer.

Abstract: An integrated modular multiple chamber vacuum processing system is disclosed. The system includes a load lock, may include an external cassette elevator, and an internal load lock wafer elevator, and also includes stations about the periphery of the load lock for connecting one, two or several vacuum process chambers to the load lock chamber. A robot is mounted within the load lock and utilizes a concentric shaft drive system connected to an end effector via a dual four-bar link mechanism for imparting selected R-.theta. movement to the blade to load and unload wafers at the external elevator, internal elevator and individual process chambers. The system is uniquely adapted for enabling various types of IC processing including etch, deposition, sputtering and rapid thermal annealing chambers, thereby providing the opportunity for multiple step, sequential processing using different processes.

Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer.

Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either along or in conjunction with a subsequent isotropic etch.

Abstract: A magnetic field enhanced single wafer plasma etch reactor is disclosed. The features of the reactor include an electrically-controlled stepped magnetic field for providing high rate uniform etching at high pressures; temperature controlled reactor surfaces including heated anode surfaces (walls and gas manifold) and a cooled wafer supporting cathode; and a unitary wafer exchange mechanism comprising wafer lift pins which extend through the pedestal and a wafer clamp ring. The lift pins and clamp ring are moved vertically by a one-axis lift mechanism to accept the wafer from a cooperating external robot blade, clamp the wafer to the pedestal and return the wafer to the blade. The electrode cooling combines water cooling for the body of the electrode and a thermal conductivity-enhancing gas parallel-bowed interface between the wafer and electrode for keeping the wafer surface cooled despite the high power densities applied to the electrode.