Abstract: In an example, a system includes a processor, where the processor includes a plurality of processor registers, and where the processor is configured to execute a first instruction in a first execution context. The processor is also configured to receive a PRESERVE instruction that indicates at least one processor register among the plurality of processor registers. The processor is configured to, responsive to the PRESERVE instruction, preserve parameters in the at least one processor register and clear other processor registers in the plurality of processor registers in the first execution context. The processor is also configured to execute a second instruction in a second execution context.

Abstract: An exemplary timing generator includes a coarse delay circuit configured to generate a coarse delayed rising edge signal and a coarse delayed falling edge signal from a reference timing signal; a fine delay circuit configured to generate a fine delayed rising edge signal from the coarse delayed rising edge signal and a fine delayed falling edge signal from the coarse delayed falling edge signal; an edge combiner configured to generate the timing signal based on the fine delayed rising edge signal and the fine delayed falling edge signal; and a masking circuit configured to generate a rising edge masking signal and a falling edge masking signal for controlling when the rising edges and the falling edges of the timing signal are generated.

Abstract: In one aspect, a level shifter for shifting a voltage level from a first voltage level to a second voltage level and having a predictable power-up state is provided. The level shifter comprises a first input and a second input forming a differential input to receive signals at the first voltage level, a first output and a second output forming a differential output to provide output signals at the second voltage level, and at least one circuit element coupled between the differential input and the differential output to pull the first output to a lower voltage level than the second output during power-up so that the level shifter powers-up in a desired state.

Abstract: A method of transferring charge from a photosensitive array using a plurality of vertical shift registers, each having a plurality of vertical elements including first and last vertical element is disclosed The vertical shift registers are capable of transferring charge in a first direction from the first to the last vertical element The method also includes using at least one horizontal shift register having a plurality of horizontal elements. Each of the horizontal elements is arranged to receive charge transferred from the last vertical element of a respective one of the plurality of vertical shift registers, and shift the charge in a horizontal direction. The method includes operating the horizontal shift register during a plurality of horizontal operating intervals and operating the plurality of vertical shift registers during at least a portion of the plurality of horizontal operating intervals.

Abstract: In one aspect, a method of transferring charge from a photosensitive array using a plurality of vertical shift registers each having a plurality of vertical elements including a first vertical element and a last vertical element, each of the plurality of vertical elements capable of storing charge, the plurality of vertical shifter registers, when operated, are capable of transferring charge from each of the plurality of vertical elements to a respective adjacent one of the plurality of vertical elements in a first direction from the first vertical element to the last vertical element, and using at least one horizontal shift register having a plurality of horizontal elements, each of the plurality of horizontal elements of the at least one horizontal shift register arranged to receive charge transferred from the last vertical element of a respective one of the plurality of vertical shift registers, the at least one horizontal shift register, when operated, capable of transferring charge from each of the plura

Abstract: In one aspect, a level shifter for shifting a voltage level from a first voltage level to a second voltage level and having a predictable power-up state is provided.

Abstract: A system and method for preventing unauthorized access to the software of a semiconductor device is provided. The semiconductor device of the present invention includes a memory buffer in the data path between the processor core of the device and the memory of the device. A password for providing full communication in the data path is stored in a defined location in the memory. Upon reading the memory location, the password is provided to a code security module. The password provided to the code security module is compared to a data string provided by the user. If the password and the data string match, the password data path is open for communication between the memory and the processor core. If the password and data string do not match, the password data path is closed to communication between the memory and the processor core.

Abstract: A state machine circuit may be used to control a multiplexing circuit that selects and provides respective ones of multiple input clock signals to a clock-synthesizing circuit that generates a synthesized clock signal in response to such input clock signals. The state machine circuit may, for example, be configured so that the synthesized clock signal is a spread-spectrum clock signal and/or a clock signal having a nominal frequency that is greater than a nominal frequency of each of the input clock signals.

Abstract: One embodiment of the invention is directed to a method, comprising acts of generating a plurality of delay signals, and processing at least first and second delay signals of the plurality of delay signals to generate a first timing signal. Another embodiment of the invention is directed to a timing signal generator to generate a plurality of timing signals. The circuit comprises a delay signal generator to generate a plurality of delay signals, and a clock synthesizer to generate the timing signals based on selected ones of the delay signals.

Abstract: One embodiment of the invention is directed to a method comprising an act of generating a timing signal, wherein at least some rising edges of the timing signal are based on edges of a first delay signal having a first period and a first phase, and at least some falling edges of the timing signal are based on edges of a second delay signal having a second period that is substantially the same as the first period, and a second phase that is different from the first phase. Another embodiment of the invention is directed to a programmable clock synthesizer comprising an edge-triggered circuit that receives a rising edge delay signal and a falling edge delay signal, wherein the edge-triggered circuit is adapted to generate a synthesized clock signal having rising edges triggered in response to edges of the rising edge delay signal and falling edges triggered in response to edges of the falling edge delay signal.

Abstract: One embodiment of the invention is directed to a method comprising an act of generating a timing signal, wherein at least some rising edges of the timing signal are based on edges of a first delay signal having a first period and a first phase, and at least some falling edges of the timing signal are based on edges of a second delay signal having a second period that is substantially the same as the first period, and a second phase that is different from the first phase. Another embodiment of the invention is directed to a programmable clock synthesizer comprising an edge-triggered circuit that receives a rising edge delay signal and a falling edge delay signal, wherein the edge-triggered circuit is adapted to generate a synthesized clock signal having rising edges triggered in response to edges of the rising edge delay signal and falling edges triggered in response to edges of the falling edge delay signal.

Abstract: One embodiment of the invention is directed to a method, comprising acts of generating a plurality of delay signals, and processing at least first and second delay signals of the plurality of delay signals to generate a first timing signal. Another embodiment of the invention is directed to a timing signal generator to generate a plurality of timing signals. The circuit comprises a delay signal generator to generate a plurality of delay signals, and a clock synthesizer to generate the timing signals based on selected ones of the delay signals.

Abstract: A system and method for preventing unauthorized access to the software of a semiconductor device is provided. The semiconductor device of the present invention includes a memory buffer in the data path between the processor core of the device and the memory of the device. A password for providing full communication in the data path is stored in a defined location in the memory. Upon reading the memory location, the password is provided to a code security module. The password provided to the code security module is compared to a data string provided by the user. If the password and the data string match, the password data path is open for communication between the memory and the processor core. If the password and data string do not match, the password data path is closed to communication between the memory and the processor core.

Abstract: The current flow from a temperature-variable current source to a Hall-effect element is adjusted according to sensed temperature conditions of the element to compensate for temperature-dependent changes in the magnetic-field sensitivity of the Hall-effect element and in the magnitude of the permanent magnetic fields of magnetic components sensed by the element. A trimmable resistor is connected between two external terminals of a Monolithically integrated circuit to provide external control over the sensitivity of the temperature variable current source to changing temperature conditions. The device also alternately switches the quadrature states of output and bias supply contacts of the Hall-effect element to compensate for the offset and drift thereof.