Patents by Inventor David Pardo
David Pardo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220206955Abstract: A translation lookaside buffer (TLB) having a fixed sub-TLB and a configurable sub-TLB and methods of using the TLB are provided. The TLB includes a fixed sub-TLB and a configurable sub-TLB. The fixed sub-TLB, during runtime, may store a first plurality of TLB entries corresponding to a first page size set. The configurable sub-TLB, during runtime, is configurable to store a second plurality of TLB entries of a second page size set. The second page size set includes at least a first page size of the first page size set and includes at least a second page size not of the first page size set.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Inventor: David Pardo Keppel
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Publication number: 20220058619Abstract: Registration information for a plurality of consumers is obtained at an electronic wallet platform. A mechanism is provided to integrate the electronic wallet platform with a plurality of merchants. Via the electronic wallet platform, a given one of the consumers is afforded an option to select from multiple methods to pay for a transaction with a given one of the merchants. The multiple methods are based, at least in part, on the registration information. At least one of the multiple methods includes a virtual card number. Further steps include obtaining, from the given one of the consumers, a selection of the virtual card number for payment for the transaction; and providing the given one of the merchants with the virtual card number.Type: ApplicationFiled: November 1, 2021Publication date: February 24, 2022Inventors: David Pardo, Anand Shekaran, Jose A. Alba, Michael J. Shaon, Aimee G. Musil, Michael S. Ameiss, Eric R. Kitchen
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Patent number: 11222329Abstract: Registration information for a plurality of consumers is obtained at an electronic wallet platform. A mechanism is provided to integrate the electronic wallet platform with a plurality of merchants. Via the electronic wallet platform, a given one of the consumers is afforded an option to select from multiple methods to pay for a transaction with a given one of the merchants. The multiple methods are based, at least in part, on the registration information. At least one of the multiple methods includes a virtual card number. Further steps include obtaining, from the given one of the consumers, a selection of the virtual card number for payment for the transaction; and providing the given one of the merchants with the virtual card number.Type: GrantFiled: March 15, 2013Date of Patent: January 11, 2022Assignee: MASTERCARD INTERNATIONAL INCORPORATEDInventors: David Pardo, Anand Shekaran, Jose A. Alba, Michael J. Shaon, Aimee G. Musil, Michael S. Ameiss, Eric R. Kitchen
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Patent number: 11055232Abstract: A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.Type: GrantFiled: March 29, 2019Date of Patent: July 6, 2021Assignee: Intel CorporationInventors: David Pardo Keppel, Binh Pham
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Publication number: 20190227947Abstract: A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.Type: ApplicationFiled: March 29, 2019Publication date: July 25, 2019Inventors: David Pardo Keppel, Binh Pham
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Patent number: 10168765Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.Type: GrantFiled: May 3, 2016Date of Patent: January 1, 2019Assignee: Intel CorporationInventors: David Pardo Keppel, Jawad Nasrullah
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Patent number: 10061587Abstract: A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.Type: GrantFiled: September 25, 2014Date of Patent: August 28, 2018Assignee: Intel CorporationInventors: David Pardo Keppel, Denis M. Khartikov, Fernando LaTorre, Marc Lupon, Grigorios Magklis, Naveen Neelakantam, Georgios Tournavitis, Polychronis Xekalakis
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Publication number: 20160320832Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.Type: ApplicationFiled: May 3, 2016Publication date: November 3, 2016Inventors: David Pardo Keppel, Jawad Nasrullah
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Patent number: 9477628Abstract: A collective communication apparatus and method for parallel computing systems. For example, one embodiment of an apparatus comprises a plurality of processor elements (PEs); collective interconnect logic to dynamically form a virtual collective interconnect (VCI) between the PEs at runtime without global communication among all of the PEs, the VCI defining a logical topology between the PEs in which each PE is directly communicatively coupled to a only a subset of the remaining PEs; and execution logic to execute collective operations across the PEs, wherein one or more of the PEs receive first results from a first portion of the subset of the remaining PEs, perform a portion of the collective operations, and provide second results to a second portion of the subset of the remaining PEs.Type: GrantFiled: September 28, 2013Date of Patent: October 25, 2016Assignee: Intel CorporationInventors: Allan D. Knies, David Pardo Keppel, Dong Hyuk Woo, Joshua B. Fryman
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Publication number: 20160179662Abstract: A processor includes a binary translator, a memory management unit, and a monitor unit. The binary translator includes logic to translate a region of code and to reorder translated instructions within the region to produce a transaction. The memory management unit includes logic to receive a memory instruction from the transaction to access an address in memory, determine whether the address is associated with a previous page table walk during execution of the transaction based on bits set for addresses during the previous page table walk, and allow execution of the memory instruction based upon the determination whether the address is associated with the previous page table walk. The monitor unit includes logic to specify whether a given address is associated with the previous page table walk during execution of the transaction.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: David Pardo Keppel, John H. Kelm
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Patent number: 9354694Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.Type: GrantFiled: March 14, 2013Date of Patent: May 31, 2016Assignee: Intel CorporationInventors: David Pardo Keppel, Jawad Nasrullah
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Patent number: 9342403Abstract: An apparatus and method for scrubbing spin transfer torque (STT) memory. For example, one embodiment of a apparatus comprises: a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries; and a scrub engine to ensure that the entries of the STT contain valid data, the scrub engine including analysis and processing logic to determine, for each entry, whether a specified scrubbing interval has expired and, if so, then to invalidate the entry or re-fetch data for the entry from a source and, if the scrubbing interval has not expired, then to perform error detection and/or correction on the entry.Type: GrantFiled: March 28, 2014Date of Patent: May 17, 2016Assignee: Intel CorporationInventors: David Pardo Keppel, Helia Naeimi, Jawad Nasrullah
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Patent number: 9329658Abstract: In one embodiment, a processor includes at least one sleep block and a central sleep controller. The at least one sleep block may include at least one execution unit, at least one processor component, and sleep logic. The central sleep controller may be to program the sleep logic to perform at least one sleep transition for the at least one sleep block, and to operate in a first sleep mode. The sleep logic may be to perform the at least one sleep transition for the at least one sleep block without waking the central sleep controller from the first sleep mode. Other embodiments are described and claimed.Type: GrantFiled: December 28, 2012Date of Patent: May 3, 2016Assignee: Intel CorporationInventors: David Pardo Keppel, Jawad Nasrullah
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Publication number: 20160092222Abstract: A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.Type: ApplicationFiled: September 25, 2014Publication date: March 31, 2016Inventors: David Pardo Keppel, Denis M. Khartikov, Fernando LaTorre, Marc Lupon, Grigorios Magklis, Naveen Neelakantam, Georgios Tournavitis, Polychronis Xekalakis
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Publication number: 20150278011Abstract: An apparatus and method for scrubbing spin transfer torque (STT) memory. For example, one embodiment of a apparatus comprises: a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries; and a scrub engine to ensure that the entries of the STT contain valid data, the scrub engine including analysis and processing logic to determine, for each entry, whether a specified scrubbing interval has expired and, if so, then to invalidate the entry or re-fetch data for the entry from a source and, if the scrubbing interval has not expired, then to perform error detection and/or correction on the entry.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Inventors: DAVID PARDO KEPPEL, HELIA NAEIMI, JAWAD NASRULLAH
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Publication number: 20150095542Abstract: A collective communication apparatus and method for parallel computing systems. For example, one embodiment of an apparatus comprises a plurality of processor elements (PEs); collective interconnect logic to dynamically form a virtual collective interconnect (VCI) between the PEs at runtime without global communication among all of the PEs, the VCI defining a logical topology between the PEs in which each PE is directly communicatively coupled to a only a subset of the remaining PEs; and execution logic to execute collective operations across the PEs, wherein one or more of the PEs receive first results from a first portion of the subset of the remaining PEs, perform a portion of the collective operations, and provide second results to a second portion of the subset of the remaining PEs.Type: ApplicationFiled: September 28, 2013Publication date: April 2, 2015Inventors: Allan D. Knies, David Pardo Keppel, Dong Hyuk Woo, Joshua B. Fryman
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Publication number: 20150052010Abstract: Local shipping addresses in a first country are assigned to consumers having physical addresses in one or more different countries. In connection with an on-line shopping session at an e-commerce retailer, a request is obtained, from the e-commerce retailer, for a corresponding one of the local shipping addresses; the same is supplied to the e-commerce retailer in response to the request. Product information and an indication of a desired form of shipping from the e-commerce retailer to the local shipping address are obtained; as are an indication of a desired form of shipping from the local shipping address to a corresponding one of the physical addresses. An indication of an estimated fully landed cost associated with the on-line shopping session is dispatched.Type: ApplicationFiled: August 18, 2014Publication date: February 19, 2015Inventors: Jose A. Alba, Michael J. Shaon, Aimee G. Musil, Michael S. Ameiss, Eric R. Kitchen, David Pardo, Anand Shekaran
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Publication number: 20140281602Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: David Pardo Keppel, Jawad Nasrullah
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Patent number: 8812396Abstract: Local shipping addresses in a first country are assigned to a plurality of consumers having physical addresses in at least one country other than the first country. A request is obtained, from an e-commerce retailer, for a corresponding one of the local shipping addresses. Product information, an indication of a desired form of shipping from the e-commerce retailer to the corresponding one of the local shipping addresses, and an indication of a desired form of shipping from the corresponding one of the local shipping addresses to a corresponding one of the physical addresses in the at least one country other than the first country are obtained. An indication of an estimated fully landed cost associated with the on-line shopping session is dispatched.Type: GrantFiled: November 5, 2012Date of Patent: August 19, 2014Assignee: Mastercard International IncorporatedInventors: Jose A. Alba, Michael J. Shaon, Aimee G. Musil, Michael S. Ameiss, Eric R. Kitchen, David Pardo, Anand Shekaran
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Publication number: 20140189401Abstract: In one embodiment, a processor includes at least one sleep block and a central sleep controller. The at least one sleep block may include at least one execution unit, at least one processor component, and sleep logic. The central sleep controller may be to program the sleep logic to perform at least one sleep transition for the at least one sleep block, and to operate in a first sleep mode. The sleep logic may be to perform the at least one sleep transition for the at least one sleep block without waking the central sleep controller from the first sleep mode. Other embodiments are described and claimed.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: DAVID PARDO KEPPEL, JAWAD JAKE NASRULLAH