Abstract: A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.

Abstract: A fluid injection system includes an injector housing, a sleeve, and a lighting assembly. The sleeve is coupled to the injector housing and is configured to receive and secure a fluid reservoir. The lighting assembly is coupled to the injector housing. The lighting assembly includes a light source configured to illuminate an interior of the fluid reservoir by directing light emitted by the light source into the fluid reservoir.

Abstract: Apparatus and methods for page-based soft post package repair are disclosed. Based on data stored in a storage element, an address may be decoded to a prime row, a row-based redundant row, or a page-based redundant row. A match logic circuit may determine whether the address corresponds to a defective prime row and generate a match signal. A decoder can select a redundant row to be accessed instead of a prime row in response to the match signal indicating that the address data corresponding to the address to be accessed matches defective address data stored in a volatile memory. A page-based redundant row allows for page-by-page substitution for defective memory, allowing functional portions of memory to continue to be used.

Abstract: Aspects of the present disclosure are related unmanned aerial vehicles tethered to ground stations with an expendable airborne fiber-optic link. The tethers may be fiber-optic cables that can be used as a communications conduit between a ground station and a UAV for providing vehicle positioning/control information to the UAV as well as transmitting a large amount of information/data to the UAV. As the information being transmitted between to the UAV the ground station is critical, fiber-optic cables provide the bandwidth and transmission capabilities required with the added benefit of electromagnetic interference (EMI) and radio-frequency interference (RFI) immunity, making this an ideal solution for these applications.

Abstract: A power restoration system comprising a feeder, a plurality of power sources available to provide power to the feeder, a plurality of normally closed reclosing devices electrically coupled along the feeder, at least one normally open recloser electrically coupled to the feeder, and a plurality of normally closed switches electrically coupled along the feeder between each adjacent pairs of normally closed reclosing devices. Each switch is assigned a position code having a value for each of the plurality of power sources that determines when the switch will open in response to the fault current and which power source the switch is currently receiving power from, where timing control between the reclosing devices and the switches allows the switch to be selectively opened to isolate the fault within a single feeder section between each pair of adjacent switches or between each switch and a reclosing device.

Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

Abstract: Methods, systems, and devices are described for adjusting parameters of channel drivers based on temperature when a calibration component is unavailable. A memory device may determine whether a calibration component is available for use by the memory device. If not, the memory device may select an impedance setting for the driver that is based on an operating temperature of the memory device. A device or system may identify a temperature of a memory device, identify that a calibration component is unavailable to adjust a parameter of a driver of a data channel, select a value of the parameter based on the temperature and on identifying that the calibration component is unavailable, adjust the parameter of the driver of the data channel to the selected value, and transmit, by the driver operating using the selected value of the parameter, a signal over the channel.

Abstract: The present invention provides a compound of formula (1) or a pharmaceutically acceptable salt thereof; a method for manufacturing the compounds of the invention, and its therapeutic uses. The present invention further provides a combination of pharmacologically active agents and a pharmaceutical composition.

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

Abstract: Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.

Abstract: Systems and methods described herein may enable memory maintenance operations to be performed on a memory device in compliance with a time interval having a duration based on a temperature of the memory device. A system may include a memory device and a memory controller communicatively coupled to the memory device. The memory controller may receive a temperature measurement indicative of a present temperature of the memory device and determine a memory management interval based on the temperature measurement. The memory controller may perform a memory management operation based on the memory management interval. Sometimes, the memory controller powers on the memory device to perform the memory management operation on the memory device.

Abstract: Embodiments relate to improving the biasing of active electronic components such as, for example, sense amplifiers. Embodiments include an adjustable bias signal generator that receives a reference signal as an input and generates a corresponding bias signal as an output. The adjustable bias signal generator may comprise a voltage driver and capacitor divider circuitry. In some embodiments, the capacitor divider circuitry is configurable by selecting specific capacitor dividers using a digital code. In other embodiments, the voltage driver is adjustable by applying different trim settings to tune the output of the voltage driver. The voltage driver may be temperature compensated by multiplexing different trim settings that correspond to different temperatures.

Abstract: The present invention provides a compound of formula (I) or a pharmaceutically acceptable salt thereof; a method for manufacturing the compounds of the invention, and its therapeutic uses. The present invention further provides a combination of pharmacologically active agents and a pharmaceutical composition.

Abstract: A system (100) for providing a timing signal with tunable temperature dependency in an electronic device may include a timing circuit (102) and an initial setting circuit (104). The timing circuit (102) may include a delay stage (106) and a gate stage (108). The delay stage (106) may be configured to receive an input signal and to produce a delayed signal by introducing a delay to the input signal. The gate stage (108) may be configured to receive the delayed signal and a threshold setting signal, to produce an output signal using the delayed signal and a logic threshold, and to set an initial value of the logic threshold according to the threshold setting signal. The initial setting circuit (104) may be configured to allow the threshold setting signal to be tuned for providing the time delay with a specified temperature dependency.

Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).

Abstract: A power restoration system comprising a feeder, a plurality of power sources available to provide power to the feeder, a plurality of normally closed reclosing devices electrically coupled along the feeder, at least one normally open recloser electrically coupled to the feeder, and a plurality of normally closed switches electrically coupled along the feeder between each adjacent pairs of normally closed reclosing devices. Each switch is assigned a position code having a value for each of the plurality of power sources that determines when the switch will open in response to the fault current and which power source the switch is currently receiving power from, where timing control between the reclosing devices and the switches allows the switch to be selectively opened to isolate the fault within a single feeder section between each pair of adjacent switches or between each switch and a reclosing device.

Abstract: The 2D barcode at the base of a sample tube is protected from frosting by an air pocket within a wall of high thermal conductivity material that surrounds the barcode. The wall is of thermal conductivity greater than 14W/m K and preferably greater than 200W/m K. The wall may be formed as a skirt extending from the base of the sample tube or as a part of a supporting rack. The wall, cooled by the sample tube and the frozen sample within the tube, collects frost that would otherwise collect on the 2D barcode and deflects the flow of moist air that would otherwise flow against the barcode.

Abstract: Methods, systems, and devices are described for adjusting parameters of channel drivers based on temperature when a calibration component is unavailable. A memory device may determine whether a calibration component is available for use by the memory device. If not, the memory device may select an impedance setting for the driver that is based on an operating temperature of the memory device. A device or system may identify a temperature of a memory device, identify that a calibration component is unavailable to adjust a parameter of a driver of a data channel, select a value of the parameter based on the temperature and on identifying that the calibration component is unavailable, adjust the parameter of the driver of the data channel to the selected value, and transmit, by the driver operating using the selected value of the parameter, a signal over the channel.

Abstract: Error correction procedures for a memory device including a memory die having an array of memory cells including a plurality of banks are described. The memory die includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.