Patents by Inventor David Pritchard

David Pritchard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180215488
    Abstract: A unit for mixing and dispensing an aerosol precursor composition, and containers to be dispensed therefrom. The unit includes a plurality of bulk material filling stations, the plurality of bulk material filling stations have at least one first filling station with aerosol former and at least one second filling station with a flavor material for creating the aerosol precursor. The unit also includes a bulk consumable pack staging a plurality of containers configured to receive the aerosol precursor, and a robot configured to retrieve a container from the bulk consumable pack and move the container through at least two dimensions to stop at least two of the plurality of bulk material filling stations.
    Type: Application
    Filed: February 2, 2017
    Publication date: August 2, 2018
    Inventors: Andries Don Sebastian, Charles Jacob Novak, III, Alvaro Gonzalez-Parra, Eugenia Theophilus, Marielle Anitra Keyna des Etages, Joseph Dominique, Wesley Steven Jones, Bradley Phillips, Mark Dockrill, Simon A. English, Simon Philip Adam Higgins, Thomas Crugnale, Jeffrey Hughes, Robert Neil, David Pritchard
  • Publication number: 20180197882
    Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Inventors: David PRITCHARD, Lixia LEI, Deniz E. CIVAY, Scott D. LUNING, Neha NAYYAR
  • Patent number: 9973904
    Abstract: A computing platform may receive, from a plurality of computing systems, data identifying permissions of a plurality of users to access one or more resources of the plurality of computing systems. The computing platform may identify, from amongst the plurality of users, a plurality of groups of users. The computing platform may identify, from amongst the permissions, a plurality of sets of permissions. Each set of permissions may include permissions shared by each user of a group of users of the plurality of groups of users. The computing platform may generate a graphical depiction of the plurality of groups of users and the plurality of sets of permissions. The graphical depiction may graphically depict, for each group of the plurality of groups, one or more sets of permissions, of the plurality of sets of permissions, shared by each user of the group.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: May 15, 2018
    Assignee: Bank of America Corporation
    Inventors: Igor A. Baikalov, Armen Moloian, David Pritchard
  • Patent number: 9941301
    Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David Pritchard, Lixia Lei, Deniz E. Civay, Scott D. Luning, Neha Nayyar
  • Patent number: 9666488
    Abstract: A method of forming a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains and the resulting device are provided. Embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on a p-side of the semiconductor layer and a nFET gate on a n-side of the semiconductor layer; forming a gate contact between the pFET gate and the nFET gate; forming raised source/drains on opposite sides of each of the pFET and nFET gates; and forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and below the gate contact between the pFET and nFET gates.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: May 30, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tuhin Guha Neogi, David Pritchard, Scott Luning, Guillaume Bouche, David Doman
  • Patent number: 9472455
    Abstract: A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: October 18, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jason E. Stephens, Lei Yuan, Lixia Lei, David Pritchard, Tuhin Guha Neogi
  • Patent number: 9465907
    Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ahmed Hassan, Nader Magdy Hindawy, Vikrant Chauhan, Jason Eugene Stephens, David Pritchard, Abbas Guvenilir, David E. Brown, Terry J. Bordelon, Jr.
  • Patent number: 9436081
    Abstract: A method is provided, in which a masking reticle including a plurality of pattern blocks is modified, the modifying including: identifying a first pattern block and a second pattern block of the plurality of pattern blocks where at least a first portion of the first pattern block and a second portion of the second pattern block are in parallel relation; and reducing a length of the first portion of the first pattern block when a transverse separation S between corresponding length edges of the first portion of the first pattern block the second portion of the second pattern block falls within a pre-defined forbidden pitch range for the masking reticle. The method may include repeating the identifying and reducing of pairs of pattern blocks on the mask reticle to remove portions of pattern block pairs spaced apart by a transverse separation falling within a forbidden-pitch range.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jason Eugene Stephens, David Pritchard
  • Publication number: 20160080224
    Abstract: A computing platform may receive, from a plurality of computing systems, data identifying permissions of a plurality of users to access one or more resources of the plurality of computing systems. The computing platform may identify, from amongst the plurality of users, a plurality of groups of users. The computing platform may identify, from amongst the permissions, a plurality of sets of permissions. Each set of permissions may include permissions shared by each user of a group of users of the plurality of groups of users. The computing platform may generate a graphical depiction of the plurality of groups of users and the plurality of sets of permissions. The graphical depiction may graphically depict, for each group of the plurality of groups, one or more sets of permissions, of the plurality of sets of permissions, shared by each user of the group.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: Igor A. Baikalov, Armen Moloian, David Pritchard
  • Publication number: 20160026748
    Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.
    Type: Application
    Filed: July 25, 2014
    Publication date: January 28, 2016
    Inventors: Ahmed Hassan, Nader Magdy Hindawy, Vikrant Chauhan, Jason Eugene Stephens, David Pritchard, Abbas Guvenilir, David E. Brown, Terry J. Bordelon, Jr.
  • Patent number: 9224617
    Abstract: A method is provided for fabricating cross-coupled line segments for use, for instance, as a hard mask in fabricating cross-coupled gates of two or more transistors. Fabricating the structure includes: providing a sacrificial mandrel on the substrate, the sacrificial mandrel including a transverse gap through the mandrel separating the sacrificial mandrel into a first mandrel portion and a second mandrel portion; providing a sidewall spacer along sidewalls of the sacrificial mandrel, where sidewall spacers along sidewalls of the first mandrel portion and the second mandrel portion merge within the transverse gap and form a crossbar; and removing the sacrificial mandrel and selectively cutting the sidewall spacers to define the cross-coupled line segments from the sidewall spacers and crossbar. The transverse gap may be provided by directly printing the first and second mandrel portions spaced apart, or by cutting the sacrificial mandrel to provide the gap.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: David Pritchard, Jason E. Stephens
  • Publication number: 20150287604
    Abstract: A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.
    Type: Application
    Filed: April 7, 2014
    Publication date: October 8, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jason E. STEPHENS, Lei YUAN, Lixia LEI, David PRITCHARD, Tuhin Guha NEOGI
  • Publication number: 20150261084
    Abstract: A method is provided, in which a masking reticle including a plurality of pattern blocks is modified, the modifying including: identifying a first pattern block and a second pattern block of the plurality of pattern blocks where at least a first portion of the first pattern block and a second portion of the second pattern block are in parallel relation; and reducing a length of the first portion of the first pattern block when a transverse separation S between corresponding length edges of the first portion of the first pattern block the second portion of the second pattern block falls within a pre-defined forbidden pitch range for the masking reticle. The method may include repeating the identifying and reducing of pairs of pattern blocks on the mask reticle to remove portions of pattern block pairs spaced apart by a transverse separation falling within a forbidden-pitch range.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 17, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jason Eugene STEPHENS, David PRITCHARD
  • Publication number: 20150214064
    Abstract: A method is provided for fabricating cross-coupled line segments for use, for instance, as a hard mask in fabricating cross-coupled gates of two or more transistors. Fabricating the structure includes: providing a sacrificial mandrel on the substrate, the sacrificial mandrel including a transverse gap through the mandrel separating the sacrificial mandrel into a first mandrel portion and a second mandrel portion; providing a sidewall spacer along sidewalls of the sacrificial mandrel, where sidewall spacers along sidewalls of the first mandrel portion and the second mandrel portion merge within the transverse gap and form a crossbar; and removing the sacrificial mandrel and selectively cutting the sidewall spacers to define the cross-coupled line segments from the sidewall spacers and crossbar. The transverse gap may be provided by directly printing the first and second mandrel portions spaced apart, or by cutting the sacrificial mandrel to provide the gap.
    Type: Application
    Filed: January 29, 2014
    Publication date: July 30, 2015
    Applicant: Globalfoundries Inc.
    Inventors: David PRITCHARD, Jason E. STEPHENS
  • Patent number: 9045001
    Abstract: An axle shaft is fabricated from two separate pieces. The axle shaft is comprised of an axle shaft body having a forged initial flange portion formed at one end. An axle shaft flange, fabricated by stamping or casting for example, is secured to the forged initial flange portion at a weld interface to form a finished axle shaft.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: June 2, 2015
    Assignee: ArvinMeritor Technology, LLC
    Inventors: Raymond A. Milio, Hugh David Pritchard, Antonio Coletta, Licinio Curti, Kenneth Kinfun Yu, Harry William Trost, Michael Vedder, Daniel James Crabtree, Jack R. McKenzie, David Gonska
  • Patent number: 9027310
    Abstract: The method and apparatus relates to providing a slit, perforation, line of weakness or similar structure in a flange of a zipper for a reclosable package or bag, including a high-capacity zipper. The slit, perforation, line of weakness or similar structure provides an opening for filling the reclosable package or bag without the need to separate the zipper profiles from each other. After filling, the opening is sealed and the cosmetic appearance of the reclosable package or bag is maintained.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: May 12, 2015
    Assignee: Illinois Tool Works Inc.
    Inventors: Glyn Russell, Charles Greco, Lars Wihlborg, Robert J. Coulton, David Anzini, Brian Ehrhardt, Francis Olajide, Jr., Eric Plourde, David Pritchard
  • Publication number: 20140227770
    Abstract: A sample collection container and a cartridge system employ reagent bodies having reagents confined by a restraining agent. The sample collection container comprises one or more reagent bodies, each having one or more reagents confined by a restraining agent. The restraining agent is capable of being broken down to release the reagents which are dispersed through the restraining agent. The cartridge system comprises a reagent component for storing reagents and a processing component for processing the reagents in an assay. At least one of the components includes one or more reagent bodies, each having one or more reagents confined by a restraining agent capable of being broken down. The reagent component and the processing component are configured to be coupled together to form a cartridge, the reagent component and/or the processing component having at least one compartment to accept waste from the assay.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 14, 2014
    Applicant: Scitech Corporation
    Inventors: Prabhjyot Dehal, David Pritchard, Claire Geekie
  • Patent number: 8740263
    Abstract: A latch assembly is provided, the latch assembly having: a chassis, a latch bolt having a closed position and an open position, a pawl having an engaged position and a disengaged position, an eccentric arrangement defining an eccentric axis and a pawl axis remote from the eccentric axis, wherein when the pawl moves from the engaged position to the disengaged position the eccentric arrangement rotates about the eccentric axis to move the pawl axis from a first pawl axis position to a second pawl axis position, a retaining mechanism having a retaining position at which the pawl axis is held in the first pawl axis position and having a non-retaining position at which the pawl axis is allowed to move to the second pawl axis position, a release lever configured to move the retaining mechanism between the retaining position and the non-retaining position.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: June 3, 2014
    Assignee: Inteva Products, LLC
    Inventors: Hardev Singh, Peter Coleman, David Peatey, Andrew Fairey, John Gorton, Michael Smith, Patrice Cardine, Samuel Hall, Paul Norman, David Pritchard
  • Patent number: 8669110
    Abstract: Provided is a sample collection container comprising one or more reagent bodies, wherein each body comprises one or more reagents confined by a restraining agent, wherein the restraining agent is capable of being broken down to release the one or more reagents, and wherein the one or more reagents are dispersed through the restraining agent.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: March 11, 2014
    Inventors: Prabhjyot Dehal, David Pritchard, Claire Geekie
  • Publication number: 20130047553
    Abstract: The method and apparatus relates to providing a slit, perforation, line of weakness or similar structure in a flange of a zipper for a reclosable package or bag, including a high-capacity zipper. The slit, perforation, line of weakness or similar structure provides an opening for filling the reclosable package or bag without the need to separate the zipper profiles from each other. After filling, the opening is sealed and the cosmetic appearance of the reclosable package or bag is maintained.
    Type: Application
    Filed: February 15, 2012
    Publication date: February 28, 2013
    Applicant: ILLINOIS TOOL WORKS INC.
    Inventors: Glyn Russell, Charles Greco, Lars Wihlborg, Robert J. Coulton, David Anzini, Brian Ehrhardt, Francis Olajide, JR., Eric Plourde, David Pritchard