Patents by Inventor David R. Brown

David R. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS AND SYSTEMS FOR USING STATE VECTOR DATA IN A STATE MACHINE ENGINE
    Publication number: 20190235766
    Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: David R. Brown, Harold B Noyes
  • Methods and systems for handling data received by a state machine engine
    Patent number: 10366009
    Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes, Inderjit Singh Bains
  • Shared address counters for multiple modes of operation in a memory device
    Patent number: 10346244
    Abstract: As described above, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of a memory array. To facilitate this functionality, a command controller may be provided, including one or more individual controllers to control the address sequencing when a particular mode entry command (e.g., Fast Zero or ECS) is received. In order to generate internal addresses to be accessed sequentially, one or more counters may also be provided. Advantageously, the counters may be shared such that they can be used in any mode of operation that may require address sequencing of all or large portions of the memory array, such as the Fast Zero mode or the ECS mode.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: David R. Brown
  • CAPTURE OF GROUND TRUTHED LABELS OF PLANT TRAITS METHOD AND SYSTEM
    Publication number: 20190200535
    Abstract: In embodiments, acquiring sensor data associated with a plant growing in a field, and analyzing the sensor data to extract, while in the field, one or more phenotypic traits associated with the plant from the sensor data. Indexing, while in the field, the one or more phenotypic traits to one or both of an identifier of the plant or a virtual representation of a part of the plant, and determining one or more plant insights based on the one or more phenotypic traits, wherein the one or more plant insights includes information about one or more of a health, a yield, a planting, a growth, a harvest, a management, a performance, and a state of the plant. One or more of the health, yield, planting, growth, harvest, management, performance, and the state of the plant are included in a plant insights report that is generated.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: William R. Regan, Matthew A. Bitterman, Benoit G. Schillings, David R. Brown, Elliott Grant
  • System and method for individual addressing
    Patent number: 10339071
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • SYSTEMS AND METHODS FOR WRITING ZEROS TO A MEMORY ARRAY
    Publication number: 20190179552
    Abstract: A memory device may include a memory array, which may also include, multiple memory cells. The memory device may also include one or more counters designed to generate internal memory addresses to sequentially access the memory cells and facilitate writing logical zeros to all of the memory cells.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventors: Byung S. Moon, Gary L. Howe, Harish N. Venkata, David R. Brown
  • SYSTEMS AND METHODS FOR IMPROVING WRITE PREAMBLES IN DDR MEMORY DEVICES
    Publication number: 20190164593
    Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.
    Type: Application
    Filed: November 29, 2017
    Publication date: May 30, 2019
    Inventors: Daniel B. Penney, David R. Brown, Gary L. Howe
  • System and method for individual addressing
    Patent number: 10268602
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • Methods and systems for using state vector data in a state machine engine
    Patent number: 10254976
    Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes
  • METHODS AND APPARATUSES FOR REDUCING POWER CONSUMPTION IN A PATTERN RECOGNITION PROCESSOR
    Publication number: 20190095497
    Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Harold B Noyes, David R. Brown
  • SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING
    Publication number: 20190087360
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Application
    Filed: December 10, 2018
    Publication date: March 21, 2019
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B. Noyes
  • SHARED ADDRESS COUNTERS FOR MULTIPLE MODES OF OPERATION IN A MEMORY DEVICE
    Publication number: 20190050284
    Abstract: As described above, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of a memory array. To facilitate this functionality, a command controller may be provided, including one or more individual controllers to control the address sequencing when a particular mode entry command (e.g., Fast Zero or ECS) is received. In order to generate internal addresses to be accessed sequentially, one or more counters may also be provided. Advantageously, the counters may be shared such that they can be used in any mode of operation that may require address sequencing of all or large portions of the memory array, such as the Fast Zero mode or the ECS mode.
    Type: Application
    Filed: August 10, 2017
    Publication date: February 14, 2019
    Inventor: David R. Brown
  • Modular lateral hip augments
    Patent number: 10188520
    Abstract: An implant for a hip can include a lateral augment adapted to be coupled to a lateral side of a femoral body implant. The lateral augment can include a body portion having a first surface, a second surface opposite the first surface, and a protrusion extending from the second surface. The protrusion can have a shape adapted to mate with a complementary shaped recess formed in the lateral side of the femoral body implant. An aperture can be positioned in the body portion and extend through the protrusion. A fastener can be received through the aperture and adapted to be threadably secured to the lateral bore. The fastener can be configured to have a length sufficient to pass through a portion of a greater trochanter for securing the portion of the greater trochanter and the lateral augment to the femoral body implant.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: January 29, 2019
    Assignee: Biomet Manufacturing, LLC
    Inventors: Aaron P. Smith, Tyler D. Witt, Hugh Apthorp, Keith R. Berend, Andrew Freiberg, John Barrington, David R. Brown
  • Methods and apparatuses for reducing power consumption in a pattern recognition processor
    Patent number: 10157208
    Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown
  • METHODS AND APPARATUSES FOR PROVIDING DATA RECEIVED BY A STATE MACHINE ENGINE
    Publication number: 20180341612
    Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.
    Type: Application
    Filed: August 2, 2018
    Publication date: November 29, 2018
    Inventors: David R. Brown, Harold B. Noyes, Inderjit S. Bains
  • VALIDATION OF A SYMBOL RESPONSE MEMORY
    Publication number: 20180322006
    Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 8, 2018
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • Knee prosthesis systems and methods
    Patent number: 10064733
    Abstract: A knee prosthesis system constructed in accordance to one example of the present disclosure can include a femoral component, a tibial component, a first femoral component insert, a second femoral component insert, a first tibial bearing, and a second tibial bearing. The knee prosthesis system may be configured in one of a non-hinged configuration and a second hinged configuration. In the first non-hinged configuration, the first femoral component insert is positioned relative to the femoral component and the first tibial bearing is positioned onto the tibial component. In the second hinged configuration, the second femoral component insert is positioned relative to the femoral component and the second tibial bearing is positioned onto the tibial component.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: September 4, 2018
    Assignee: Biomet Manufacturing, LLC
    Inventors: Robert Metzger, Andrew L. Pierce, David R. Brown, Brian M. May, Joshua R. Porter, Larabeth G. Ryan
  • Methods and apparatuses for providing data received by a state machine engine
    Patent number: 10067901
    Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: September 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes, Inderjit S. Bains
  • PLAN IMPLEMENTATION
    Publication number: 20180235705
    Abstract: A system and method for performing a procedure is disclosed. The procedure may include preparing one or more bones for a prosthetic implant. The method may include provide instructions to a user for using identified instruments to perform a procedure. Instructions and may be provided for settings of adjustable instruments.
    Type: Application
    Filed: March 9, 2018
    Publication date: August 23, 2018
    Inventors: David R. Brown, Troy W. Hershberger
  • Validation of a symbol response memory
    Patent number: 10019311
    Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning