Abstract: Techniques are disclosed for managing a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards, switch modules and a management controller. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards and the switch modules may be operatively connected to the midplane. The switch modules may be configured to switch network traffic for the one or more server cards. The management controller may be configured to manage the switch modules via the fabric interconnect.

Abstract: Techniques are provided for packet routing in a distributed network switch. The distributed network switch includes multiple switch modules operatively connected to one another, and each switch module includes multiple bridge elements and a management controller. In one embodiment, a shared interface routing (SIR) framework is provided that includes an analysis and bifurcation layer, at least one packet interface, and an analysis assist layer. A packet is received over a first logical network and via a physical port, the packet being destined for at least a first application executing on the management controller. The analysis assist layer analyzes the packet to determine a reason code to assign to the packet. The analysis and bifurcation layer then analyzes the packet based at least in part on the reason code.

Abstract: Techniques are provided for packet routing in a distributed network switch. The distributed network switch includes multiple switch modules operatively connected to one another, and each switch module includes multiple bridge elements and a management controller. In one embodiment, a shared interface routing (SIR) framework is provided that includes an analysis and bifurcation layer and at least one packet interface. A packet is received over a first logical network and via a physical port, the packet being destined for at least a first application executing on the management controller. The analysis and bifurcation layer analyzes the packet and sends the packet to the packet interface, which then routes the packet to the first application.

Abstract: Systems and methods to forward data frames are described. A particular method may include receiving a data frame at a switch of a plurality of networked switches coupled to a plurality of server computers. The data frame may be forwarded from a controlling bridge coupled to the plurality of networked switches. The data frame may be determined to include management data, and an operating parameter of the switch may be modified.

Abstract: A distributed switch may include a plurality of special-purpose processors that control the different functions of the switch. To enable some special services, however, the distributed switch may need one of these processors to perform the role of a master. When a processor is powered on, the processor may publish a corresponding unique ID. Before electing the master, the special-purpose processors may use a discovery process to identify the network topology of the switch and evaluate the published IDs to determine which processor should be the master. If all the processors nominate the same master processor, then that processor is elected as the master and may finish configuring the distributed switch to enable the special services.

Abstract: The different switch modules making up a distributed virtual switch may route configuration commands for hardware resources to different modules within the distributed switch using a distribution and routing layer. At least one of the switch modules maintains a routing table that defines which switch modules are responsible for which hardware resources. The switch module uses the routing tables to forward the commands on the distribution and routing layer to the responsible switch module which then ensures that the relevant hardware resources are configured.

Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.

Abstract: In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.

Abstract: Systems and methods to forward data frames are provided. A particular method may include evaluating address data of a first data frame at a first virtual bridge coupled to a first virtual machine of a first server computer of a plurality of server computers. Based upon the evaluation at the first virtual bridge, the first data frame may be forwarded to a second virtual bridge associated with an adapter that is coupled to the first virtual machine. The address data of the first data frame may be evaluated at the second virtual bridge. Based upon the evaluation, the data frame may be forwarded to a third virtual bridge configured to forward the data frame based upon the address data to a second server computer of the plurality of server computers.

Abstract: Systems and methods to forward data frames are described. A particular method may include generating a plurality of management frames at a controlling bridge. The management frames may include routing information. The plurality of management frames may be communicated to a plurality of bridge elements coupled to a plurality of server computers. The plurality of bridge elements are each configured to selectively forward a plurality of data frames according to the routing information.

Abstract: In an embodiment, a translation of a hierarchical MMIO address range to a physical MMIO address range and an identifier of a bridge in a south chip are written to a north chip. A transaction is received that comprises a hierarchical MMIO address. The hierarchical MMIO address that is within the hierarchical MMIO address range is replaced in the transaction with the identifier of the bridge and with a physical MMIO address that is within the physical MMIO address range in the south chip. The transaction is sent to the device that is connected to the bridge in the south chip. The physical MMIO address range specifies a range of physical MMIO addresses in memory in the device.

Abstract: Systems and methods to remotely configure adapters are described. A particular method may include generating a management frame at a controlling bridge. The management frame may include instructions to configure an operating parameter of the adapter. The management frame may be communicated to a bridge element of a plurality of interconnected bridge elements in communication with the controlling bridge. The bridge element may be coupled to the adapter, and the operating parameter of the adapter may be configured.

Abstract: Techniques are disclosed for reducing impact of a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card.

Abstract: Techniques are disclosed for reducing impact of a switch failure and/or a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card. The server system may further include an interconnect between the first interposer card and a second interposer card.

Abstract: Techniques are disclosed for managing a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards, switch modules and a management controller. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards and the switch modules may be operatively connected to the midplane. The switch modules may be configured to switch network traffic for the one or more server cards. The management controller may be configured to manage the switch modules via the fabric interconnect.

Abstract: Techniques are disclosed for reducing impact of a switch failure in a switch fabric. In one embodiment, a server system is provided that includes a midplane, one or more server cards and one or more switch cards. The midplane may include a fabric interconnect for a switch fabric. The one or more server cards may be coupled with the midplane, where each server card is hot-swappable from the midplane. The one or more switch cards may also be coupled with the midplane, where each switch card is also hot-swappable from the midplane. Each switch card includes one or more switch modules, and each switch module is configured to switch network traffic for at least one server card.

Abstract: In an embodiment a translation of RID (requester identifier) ranges to identifiers of north chips is stored into a south chip. A command that comprises a command RID is received at the south chip from a device. In response, a RID range is determined that encompasses the command RID, and a north chip identifier is found that is assigned a virtual function identified by the command RID. The command is sent from the south chip to the north chip identified by the north chip identifier. The translation comprises a RID compare value and a RID mask. A determination is made that the RID range encompasses the command RID by performing a logical-and operation on the command RID and the RID mask and comparing a result of the logical-and operation to the RID compare value.

Abstract: In an embodiment, a translation of a physical bus number to a hierarchical bus number is written to a south chip. The south chip receives a configuration write command that comprises a physical bus number. The south chip sends the configuration write command to a device via the bus identified by the physical bus number, and the device stores the physical bus number in the device. In response to a received message from a device that comprises the physical bus number, the south chip replaces the physical bus number in the message with the hierarchical bus number. The south chip sends the message to a north chip via a point-to-point serial link. Both the physical bus number and the hierarchical bus number identify a bus with which the device connects to a bridge in the south chip.

Abstract: In an embodiment, a command is received that requests movement of ownership of a target device from an origin compute element to a destination compute element. From the origin compute element, a translation of a virtual bridge identifier to a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range is removed. To the destination compute element, a translation of the target virtual bridge identifier to a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range is added. From a south chip that comprises the target virtual bridge, a translation of the target virtual bridge identifier to an identifier of the origin compute element is removed. To the south chip, a translation of the target virtual bridge identifier to an identifier of the destination compute element is added.

Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.