Patents by Inventor David R. Hembree

David R. Hembree has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120288997
    Abstract: A method for fabricating a stacked semiconductor system with encapsulated through wire interconnects includes providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The method also includes stacking two or more substrates and electrically connecting the through wire interconnects on the substrates.
    Type: Application
    Filed: June 27, 2012
    Publication date: November 15, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: DAVID R. HEMBREE, Alan G. Wood
  • Publication number: 20120228781
    Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a compressed wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate.
    Type: Application
    Filed: May 25, 2012
    Publication date: September 13, 2012
    Inventors: Alan G. Wood, David R. Hembree
  • Patent number: 8217510
    Abstract: A semiconductor module system includes a module substrate and first and second semiconductor components stacked on the module substrate. The stacked semiconductor components include through wire interconnects that form an internal signal transmission system for the module system. Each through wire interconnect includes a via, a wire in the via and first and second contacts on the wire.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: July 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 8193646
    Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: June 5, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, David R. Hembree
  • Publication number: 20120135567
    Abstract: Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The first external contacts are operatively coupled to the terminals on the support member. The assembly also includes a second microelectronic die having integrated circuitry and second external contacts electrically coupled to the first external contacts. The first die is between the support member and the second die. The assembly can further include a heat transfer unit between the first die and the second die. The heat transfer unit includes a first heat transfer portion, a second heat transfer portion, and a gap between the first and second heat transfer portions such that the first external contacts and the second external contacts are aligned with the gap.
    Type: Application
    Filed: February 6, 2012
    Publication date: May 31, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Salman Akram, David R. Hembree
  • Publication number: 20120043670
    Abstract: A semiconductor module system includes a module substrate and first and second semiconductor components stacked on the module substrate. The stacked semiconductor components include through wire interconnects that form an internal signal transmission system for the module system. Each through wire interconnect includes a via, a wire in the via and first and second contacts on the wire.
    Type: Application
    Filed: October 31, 2011
    Publication date: February 23, 2012
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 8120167
    Abstract: A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Publication number: 20120032182
    Abstract: A solid state light (“SSL”), a solid state emitter (“SSE”), and methods of manufacturing SSLs and SSEs. In one embodiment, an SSL comprises a packaging substrate having an electrical contact and a light emitting structure having a front side and a back side. The back side of the light emitting structure is superimposed with the electrical contact of the packaging substrate. The SSL can further include a temperature control element aligned with the light emitting structure and the electrical contact of the packaging substrate.
    Type: Application
    Filed: August 9, 2010
    Publication date: February 9, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Scott E. Sills, David R. Jenkins, David R. Hembree
  • Patent number: 8111515
    Abstract: Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The first external contacts are operatively coupled to the terminals on the support member. The assembly also includes a second microelectronic die having integrated circuitry and second external contacts electrically coupled to the first external contacts. The first die is between the support member and the second die. The assembly can further include a heat transfer unit between the first die and the second die. The heat transfer unit includes a first heat transfer portion, a second heat transfer portion, and a gap between the first and second heat transfer portions such that the first external contacts and the second external contacts are aligned with the gap.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: February 7, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, David R. Hembree
  • Patent number: 8053909
    Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: November 8, 2011
    Assignee: Micron Technology, Inc.
    Inventor: David R. Hembree
  • Publication number: 20110175223
    Abstract: A stacked semiconductor component includes a semiconductor substrate having a substrate contact, a substrate opening extending to an inner surface of the substrate contact, and a conductive interconnect comprising a wire in the substrate opening having a wire bonded connection with the inner surface of the substrate contact. The stacked semiconductor component also includes a second substrate stacked on the semiconductor substrate having a contact bonded to the conductive interconnect on the semiconductor substrate. The second substrate can also include conductive interconnects in the form of wire bonded wires, and the stacked semiconductor substrate can include a third semiconductor substrate stacked on the second substrate.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 21, 2011
    Inventors: Alan G. Wood, William M. Hiatt, David R. Hembree
  • Publication number: 20110157455
    Abstract: A method and apparatus providing a lens master device and use of the same to form a lens template and/or a lens structure. The method includes obtaining a plurality of individual lens masters, each of which has a shaped portion defining at least a portion of a lens structure to be formed. The lens masters are affixed onto a supporting structure to form a lens master device.
    Type: Application
    Filed: March 7, 2011
    Publication date: June 30, 2011
    Inventors: David R. Hembree, Steve Oliver
  • Patent number: 7960829
    Abstract: A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion that extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member that substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: June 14, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Warren M. Farnworth, David R. Hembree, Sidney B. Rigg, William M. Hiatt, Peter Benson, Kyle K. Kirby, Salman Akram
  • Patent number: 7956443
    Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: June 7, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Charles M. Watkins, Mark Hiatt, David R. Hembree, James M. Wark, Warren M. Farnworth, Mark E. Tuttle, Sidney B. Rigg, Steven D. Oliver, Kyle K. Kirby, Alan G. Wood, Lu Velicky
  • Patent number: 7951702
    Abstract: A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: May 31, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, William M. Hiatt, David R. Hembree
  • Publication number: 20110108959
    Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.
    Type: Application
    Filed: January 17, 2011
    Publication date: May 12, 2011
    Inventor: David R. Hembree
  • Publication number: 20110111561
    Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.
    Type: Application
    Filed: January 14, 2011
    Publication date: May 12, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Owen R. Fay, Warren M. Farnworth, David R. Hembree
  • Patent number: 7935991
    Abstract: A semiconductor component includes a semiconductor substrate having at least one conductive interconnect on the backside thereof bonded to an inner surface of a substrate contact. A stacked semiconductor component includes multiple semiconductor components in a stacked array having bonded connections between conductive interconnects on adjacent components. An image sensor semiconductor component includes a semiconductor substrate having light detecting elements on the circuit side, and conductive interconnects on the backside.
    Type: Grant
    Filed: May 3, 2008
    Date of Patent: May 3, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, William M. Hiatt, David R. Hembree
  • Patent number: 7919846
    Abstract: A stacked semiconductor component includes a plurality of semiconductor substrates in a stacked array and a continuous wire extending through aligned vias on the semiconductor substrates of the stacked array in electrical contact with contacts on the semiconductor substrates. A method for fabricating the semiconductor component includes the steps of stacking the semiconductor substrates in a stacked array with aligned vias; threading a wire through the aligned vias; and forming a plurality of electrical connections between the wire and the contacts on the semiconductor substrates.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: April 5, 2011
    Assignee: Micron Technology, Inc.
    Inventor: David R. Hembree
  • Patent number: 7916396
    Abstract: A method and apparatus providing a lens master device and use of the same to form a lens template and/or a lens structure. The method includes obtaining a plurality of individual lens masters, each of which has a shaped portion defining at least a portion of a lens structure to be formed. The lens masters are affixed onto a supporting structure to form a lens master device.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Steve Oliver