Abstract: A digital computer system includes a central processor unit (CPU) and an optional co-processor unit, both connected to a local bus. The co-processor unit, when installed, fits into a socket having pins, the pins being connected to communicate with the CPU through the local bus. A presence-detect circuit is connected to the local bus and receives a signal indicating the presence of the co-processor unit in the socket. Logic circuitry receives the output signal from the presence-detect circuit and provides a READY-- signal in either the presence or absence of the co-processor unit.

Abstract: A computer system includes a first processor, a second processor, a bus shared by the first processor and the second processor, and a power on reset coordination means for the first processor and the second processor. The power on reset coordination means includes means for resetting the first processor and the second processor, and means for deasserting reset to the first processor and second processor sequentially. It should be noted that in embodiments of the present invention, some "other" processor must be "up" in order to reset the "first" processor or to deassert reset to it.

Abstract: A digital computer system has an I/O command recovery circuit for providing suitable I/O recovery time for any one of a plurality of associated peripheral devices. The circuit, transparent to both software and system execution speed, enables the digital computer system to efficiently run certain software application programs that interface with the peripheral devices and provide timing loops for setting the command recovery time. Those certain software application programs, designed for earlier and slower computer systems, run the timing loops in too short a time to provide the maximum I/O recovery time. The addition of the I/O command recovery circuit provides selectable and suitable recovery times for each of the associated peripheral devices, including no recovery time for those devices not requiring it.

Abstract: A digital computer system having a local cache memory and a system bus also has a subsystem for regulating the effective processing rate of the central processor unit (CPU) of the computer system. A programmable counter/timer is programmed by data from the CPU to provide a periodic pulse of desired periodicity and pulse width for entry into a bus controller. The bus controller arbitrates use of the system bus, sending a request signal to the CPU requesting the CPU to relinquish use of the bus and it receives an acknowledgement signal from the CPU indicating its relinquishment of use of the bus. The local cache memory is flushed through the cache controller to prevent the CPU from using the local cache memory. This causes the CPU to be periodically active when using the system bus and periodically inactive when the system bus is relinquished, thereby establishing the effective processing rate of the CPU as set by the programmable counter/timer.

Abstract: A personal computer system has an I/O channel and a memory channel with a main logic board incorporating both the I/O channel and the memory channel. The computer has eight (8) expansion slots including a dual-purpose expansion slot for providing space for selective connections of I/O devices through the use of full-length logic cards or half-length logic cards being inserted into edge connectors, High speed memory, including memory control, is mounted on the main logic board and expansion memory, controlled by the memory control is mounted on a printed circuit card that is connected to the memory channel in position within the dual-purpose expansion slot, occupying approximately one-half of that slot, thereby enabling the dual-purpose expansion slot to encompass both the expansion memory and a half-length logic card. In another embodiment, the half-length logic card and the memory card within the dual-purpose expansion slot are integrated into a single logic/memory card.