Abstract: Method and system for managing a speculative transaction in a processing unit is provided. The speculative transaction is initiated by dispatching a first instruction indicating start of the speculative transaction. One or more register file (RF) entries are marked as pre-transaction memory (PTM), in response to the initiating. At least one second instruction targeting at least one of the marked RF entries is dispatched, while the transaction is active, wherein the at least one second instruction writes new result data into the at least one RF entry. Previous result data evicted from the at least one RF entry by the new result data, is saved into a history buffer (HB) entry. The HB entry is marked as PTM, in response to the saving, wherein the processing unit, upon detecting a trigger, is rolled back to a state before the initiating the transaction by restoring the previous result data to the at least one RF entry.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: The embodiments herein generate parity check data which serves as parity-on-parity. Stated differently, the parity check data can be used to determine if parity data stored in a memory element has been corrupted. For example, after generating the parity data, a computing system may set the parity check data depending on whether there is an even or odd number of logical ones (or logical zeros) in the parity data. Thus, when the parity data is read out of the memory element, if the parity data does not include the same number of even or odd bits, the parity check data indicates to the computing system that the parity data is corrupted. In one embodiment, to reduce the likelihood that the parity check data becomes corrupted, the computing system stores this data in hardened latches which are less susceptible to soft errors than other types of memory elements.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: A split level history buffer in a central processing unit is provided. A history buffer is partitioned into a first portion and a second portion, wherein the first portion includes a first tagged instruction. A result is generated for the first tagged instruction. A determination whether a second tagged instruction is to be stored in the first portion of the history buffer is made. Responsive to the determination that the second tagged instruction is to be stored in the first portion of the history buffer, the first tagged instruction and the generated result for the first tagged instruction is written to the second portion of the history buffer.

Abstract: A split level history buffer in a central processing unit is provided. A history buffer is partitioned into a first portion and a second portion, wherein the first portion includes a first tagged instruction. A result is generated for the first tagged instruction. A determination whether a second tagged instruction is to be stored in the first portion of the history buffer is made. Responsive to the determination that the second tagged instruction is to be stored in the first portion of the history buffer, the first tagged instruction and the generated result for the first tagged instruction is written to the second portion of the history buffer.

Abstract: A split level history buffer in a central processing unit is provided. A history buffer is split into a first portion and a second portion. An instruction fetch unit fetches and tags instructions with unique tags. A register file stores tagged instructions. An execution unit generates results for tagged instructions. A first instruction is fetched, tagged, and stored in an entry of the register file. A second instruction is fetched and tagged, and then evicts the first instruction from the register file, such that the second instruction is stored in the entry of the register file. Subsequently, the first instruction is stored in an entry in the first portion of the history buffer. After a result for the first instruction is generated, the first instruction is moved from the first portion of the history buffer to the second portion of the history buffer.

Abstract: A split level history buffer in a central processing unit is provided. A history buffer is partitioned into a first portion and a second portion, wherein the first portion includes a first tagged instruction. A result is generated for the first tagged instruction. A determination whether a second tagged instruction is to be stored in the first portion of the history buffer is made. Responsive to the determination that the second tagged instruction is to be stored in the first portion of the history buffer, the first tagged instruction and the generated result for the first tagged instruction is written to the second portion of the history buffer.

Abstract: A split level history buffer in a central processing unit is provided. A history buffer is split into a first portion and a second portion. An instruction fetch unit fetches and tags instructions with unique tags. A register file stores tagged instructions. An execution unit generates results for tagged instructions. A first instruction is fetched, tagged, and stored in an entry of the register file. A second instruction is fetched and tagged, and then evicts the first instruction from the register file, such that the second instruction is stored in the entry of the register file. Subsequently, the first instruction is stored in an entry in the first portion of the history buffer. After a result for the first instruction is generated, the first instruction is moved from the first portion of the history buffer to the second portion of the history buffer.

Abstract: An approach is provided is provided in which a computing system matches a writeback instruction tag (ITAG) to an entry instruction tag (ITAG) included in an issue queue entry. The writeback ITAG is provided by a first of multiple load store units. The issue queue entry includes multiple ready bits, each of which corresponds to one of the multiple load store units. In response to matching the writeback ITAG to the entry ITAG, the computer system sets a first ready bit corresponding to the first load store unit. In turn, the computing system issues an instruction corresponding to the entry ITAG based upon detecting that each of the multiple ready bits is set.

Abstract: An approach is provided is provided in which a computing system matches a writeback instruction tag (ITAG) to an entry instruction tag (ITAG) included in an issue queue entry. The writeback ITAG is provided by a first of multiple load store units. The issue queue entry includes multiple ready bits, each of which corresponds to one of the multiple load store units. In response to matching the writeback ITAG to the entry ITAG, the computer system sets a first ready bit corresponding to the first load store unit. In turn, the computing system issues an instruction corresponding to the entry ITAG based upon detecting that each of the multiple ready bits is set.

Abstract: An approach is provided in which a computing system captures content included in a history buffer entry that corresponds to a flush ITAG. The computing system, in turn, uses an execution unit to transmit the content over a results bus to multiple registers and restore at least one of the registers accordingly.

Abstract: An approach is provided in which a computing system captures content included in a history buffer entry that corresponds to a flush ITAG. The computing system, in turn, uses an execution unit to transmit the content over a results bus to multiple registers and restore at least one of the registers accordingly.

Abstract: An approach is provided in which a mapper control unit receives dispatch information corresponding to a dispatching instruction that targets some of the register fields in a register. The mapper control unit selects, in a history buffer, an available history buffer entry that includes multiple field sets, each including an itag field. In turn, the mapper control unit modifies some of the history buffer field sets, including the itag fields, based on the existing content stored in the targeted register fields.

Abstract: The present invention provides a method of treating a skin ailment including administering to a subject in need thereof, a therapeutically effective amount of a composition including (i) a primary diamine; (ii) a secondary aromatic diamine; (iii) a polyisocyanate; and (iv) optionally, a polyol. The present invention also provides a method of forming a skin bandage.

Abstract: The present invention provides a method of treating a skin ailment including administering to a subject in need thereof, a therapeutically effective amount of a composition including (i) a primary diamine; (ii) a secondary aromatic diamine; (iii) a polyisocyanate; and (iv) optionally, a polyol. The present invention also provides a method of forming a skin bandage.

Abstract: The present invention provides a method of treating a skin ailment including administering to a subject in need thereof, a therapeutically effective amount of a composition including (i) a primary diamine; (ii) a secondary aromatic diamine; (iii) a polyisocyanate; and (iv) optionally, a polyol. The present invention also provides a method of forming a skin bandage.

Abstract: The present invention provides a method of treating a skin ailment including administering to a subject in need thereof, a therapeutically effective amount of a composition including (i) a primary diamine; (ii) a secondary aromatic diamine; (iii) a polyisocyanate; and (iv) optionally, a polyol. The present invention also provides a method of forming a skin bandage.