Abstract: The present invention relates to a system and method for non-invasively attaching components to railroad track rails. More specifically, an anchor is provided that securely fastens to the track rail in a non-invasive manner for holding one or more components relative to a surface of the track rail. In one embodiment, the non-invasive anchor utilizes a compressive force to clamp to a flange portion of the track rail. Once securely clamped to the track rail, an adjustable track engaging member is utilized to hold a component relative to the surface of the track rail. In this regard, the track engaging member may be advanced toward the track rail to compress the component between a portion of the anchor and a surface of the track rail. In another embodiment, the anchor is adhesively attachable to a surface of the track rail.

Abstract: Disclosed is a method for forming electrical interconnections between railroad track components and signal conductors/lines. In one arrangement, an electrically conductive adhesive is utilized to electrically interconnect a signal conductor to a railroad track component. In another arrangement, a clamp is utilized in conjunction with the electrically conductive adhesive that forms the electrical interconnection. The clamp maintains the signal conductor in direct contact with the surface of the railroad track component while the electrically conductive adhesive cures. In these arrangements, the use of the electrically conductive adhesive allows for making an electrical connection with a railroad component without penetrating the structure of that component. In a further arrangement, a hollow tubular connector is utilized to electrically connect two signal conductors associated with railroad track components.

Abstract: Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the mux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock.

Abstract: Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the mux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock.

Abstract: Signal alignment circuitry aligns (i e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the mux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock.

Abstract: Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the flux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock.

Abstract: The present invention provides for a method and an apparatus for routing electrical signals. The method includes accessing a plurality of electrical circuits. The apparatus includes a supervisory circuit capable of delivering two access signals from a group of first, second, third, and fourth access signals, wherein the supervisory circuit is capable of delivering one of the first and third access signals, and one of the second and fourth access signals. A plurality of electrical circuits is organized into first and second rows. A first portion of the plurality of electrical circuits in the first and second rows, is coupled to a first access signal line. A second portion of the plurality of electrical circuits in the first and second rows is coupled to a second access signal line. The first and second portions of the plurality of electrical circuits in said first row are coupled to a third access signal.