Abstract: A graphics processing pipeline comprises a tessellation stage 10 operable to tessellate a patch representing some or all of an object to be rendered, so as to generate positions for a set of vertices for one or more output primitives, and a primitive assembly stage 20 operable to assemble one or more output primitives for processing using the positions for a set of vertices generated by the tessellation stage and pre-defined information defining the connectivity between at least some of the vertices of the set of vertices.

Abstract: A graphics processing unit having a shader execution unit for executing a plurality of shader routines in order to perform a predetermined sequence of shader operations. The shader operations include a tessellation operation which receives as inputs tessellation control data and an input list of input data for M input vertices, and generates at least output data for P output vertices. For each output vertex, the controller allocates a tessellation shader routine from the set of shader routines, and the shader execution unit is configured, each time the tessellation shader routine is executed for an associated output vertex: (i) to compute, in dependence on the tessellation control data and the associated output vertex, tessellation coordinate data; and (ii) to compute from the input data for the M input vertices, and the tessellation coordinate data generated in step (i), the output data for the associated output vertex.

Abstract: A graphics processing pipeline comprises a tessellation stage 10 operable to tessellate a patch representing some or all of an object to be rendered, so as to generate positions for a set of vertices for one or more output primitives, and a primitive assembly stage 20 operable to assemble one or more output primitives for processing using the positions for a set of vertices generated by the tessellation stage and pre-defined information defining the connectivity between at least some of the vertices of the set of vertices.

Abstract: A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile 22 of a frame buffer 30 to form one or more new pixel values are stored within a tile memory 40. Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.

Abstract: A graphics processing unit having a shader execution unit for executing a plurality of shader routines in order to perform a predetermined sequence of shader operations. The shader operations include a tessellation operation which receives as inputs tessellation control data and an input list of input data for M input vertices, and generates at least output data for P output vertices. For each output vertex, the controller allocates a tessellation shader routine from the set of shader routines, and the shader execution unit is configured, each time the tessellation shader routine is executed for an associated output vertex: (i) to compute, in dependence on the tessellation control data and the associated output vertex, tessellation coordinate data; and (ii) to compute from the input data for the M input vertices, and the tessellation coordinate data generated in step (i), the output data for the associated output vertex.

Abstract: A tile-based graphics system, and method of operation of such a system, are provided for generating graphics data for a frame comprising a plurality of tiles. Graphics processing circuitry is provided which is arranged to be switched between a first mode of operation and a second mode of operation. In the first mode of operation, the graphics processing circuitry receives the plurality of graphics primitives for the frame, and performs a binning operation to determine, for each of the plurality of tiles, a tile list identifying the graphics primitives which intersect that tile. In the second mode of operation, the graphics processing circuitry receives the tile list for an allocated tile, and performs a rasterization operation to generate the graphics data for the allocated tile dependent on the tile list.

Abstract: A tile-based graphics system, and method of operation of such a system, are provided for generating graphics data for a frame comprising a plurality of tiles. Graphics processing circuitry is provided which is arranged to be switched between a first mode of operation and a second mode of operation. In the first mode of operation, the graphics processing circuitry receives the plurality of graphics primitives for the frame, and performs a binning operation to determine, for each of the plurality of tiles, a tile list identifying the graphics primitives which intersect that tile. In the second mode of operation, the graphics processing circuitry receives the tile list for an allocated tile, and performs a rasterization operation to generate the graphics data for the allocated tile dependent on the tile list.

Abstract: A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile 22 of a frame buffer 30 to form one or more new pixel values are stored within a tile memory 40. Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.