Patents by Inventor David Ross Economy
David Ross Economy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210225937Abstract: Methods, systems, and devices for via formation in a memory device are described. A memory cell stack for a memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A via may also be formed in an area outside of the memory array, and the via may protrude from a material that surrounds the via. A material may then be formed above the memory cell stack and also above the via, and the top surface of the barrier material may be planarized until at least a portion of the via is exposed. A subsequently formed material may thereby be in direct contact with the top of the via, while a portion of the initially formed material may remain above the memory cell stack.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Inventors: David Ross Economy, Andrew Leslie Beemer
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Publication number: 20210202710Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.Type: ApplicationFiled: February 19, 2021Publication date: July 1, 2021Applicant: Micron Technology, Inc.Inventors: David Ross Economy, Rita J. Klein, Jordan D. Greenlee, John Mark Meldrim, Brenda D. Kraus, Everett A. McTeer
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Publication number: 20210183651Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.Type: ApplicationFiled: November 23, 2020Publication date: June 17, 2021Inventors: David Ross Economy, Brian Beatty, John Mark Meldrim, Yongjun Jeff Hu, Jordan D. Greenlee
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Patent number: 10991425Abstract: Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.Type: GrantFiled: August 13, 2018Date of Patent: April 27, 2021Assignee: Micron Technology, Inc.Inventors: David Ross Economy, Stephen W. Russell
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Patent number: 10964621Abstract: Methods, systems, and devices for a memory device with a high resistivity thermal barrier are described. In some examples a barrier material may be positioned over a memory cell region, an oxide region, and/or a through-silicon via (TSV). The barrier may include a first region above the memory cell region and a second region above the TSV. A process, such as a plasma treatment, may be applied to the barrier, which may result in the first and second regions having different thermal resistivities (e.g., different densities). Accordingly, due to the different thermal resistivities, the memory cells may be thermally insulated from thermal energy generated in the memory device.Type: GrantFiled: May 1, 2019Date of Patent: March 30, 2021Assignee: Micron Technology, Inc.Inventors: David Ross Economy, Pengyuan Zheng
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Patent number: 10957775Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.Type: GrantFiled: July 1, 2019Date of Patent: March 23, 2021Assignee: Micron Technology, Inc.Inventors: David Ross Economy, Rita J. Klein, Jordan D. Greenlee, John Mark Meldrim, Brenda D. Kraus, Everett A. McTeer
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Patent number: 10916564Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.Type: GrantFiled: May 4, 2020Date of Patent: February 9, 2021Assignee: Micron Technology, Inc.Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
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Publication number: 20210005732Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.Type: ApplicationFiled: July 1, 2019Publication date: January 7, 2021Applicant: Micron Technology, Inc.Inventors: David Ross Economy, Rita J. Klein, Jordan D. Greenlee, John Mark Meldrim, Brenda D. Kraus, Everett A. McTeer
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Publication number: 20200350225Abstract: Methods, systems, and devices for a memory device with a high resistivity thermal barrier are described. In some examples a barrier material may be positioned over a memory cell region, an oxide region, and/or a through-silicon via (TSV). The barrier may include a first region above the memory cell region and a second region above the TSV. A process, such as a plasma treatment, may be applied to the barrier, which may result in the first and second regions having different thermal resistivities (e.g., different densities). Accordingly, due to the different thermal resistivities, the memory cells may be thermally insulated from thermal energy generated in the memory device.Type: ApplicationFiled: May 1, 2019Publication date: November 5, 2020Inventors: David Ross Economy, Pengyuan Zheng
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Publication number: 20200350226Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.Type: ApplicationFiled: May 1, 2019Publication date: November 5, 2020Inventors: Pengyuan Zheng, David Ross Economy, Yongjun J. Hu, Kent H. Zhuang, Robert K. Grubbs
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Publication number: 20200266210Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.Type: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Applicant: Micron Technology, Inc.Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
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Publication number: 20200211843Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: David Ross Economy, Brian Beatty, John Mark Meldrim, Yongjun Jeff Hu, Jordan D. Greenlee
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Patent number: 10700091Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.Type: GrantFiled: June 4, 2019Date of Patent: June 30, 2020Assignee: Micron Technology, Inc.Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
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Publication number: 20200051624Abstract: Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.Type: ApplicationFiled: August 13, 2018Publication date: February 13, 2020Inventors: David Ross Economy, Stephen W. Russell
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Patent number: 10475810Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.Type: GrantFiled: June 29, 2018Date of Patent: November 12, 2019Assignee: Micron Technology, Inc.Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim
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Publication number: 20190304996Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.Type: ApplicationFiled: June 4, 2019Publication date: October 3, 2019Applicant: Micron Technology, Inc.Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
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Patent number: 10355014Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.Type: GrantFiled: December 22, 2017Date of Patent: July 16, 2019Assignee: Micron Technology, Inc.Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
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Publication number: 20190198519Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
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Publication number: 20180308861Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.Type: ApplicationFiled: June 29, 2018Publication date: October 25, 2018Applicant: Micron Technology, Inc.Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim
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Patent number: 10014319Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.Type: GrantFiled: August 17, 2017Date of Patent: July 3, 2018Assignee: Micron Technology, Inc.Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim