Abstract: A transition metal hexacyanometallate (TMHCM)-conductive polymer (CP) composite electrode is provided. The battery electrode is made up of a current collector and a transition metal hexacyanometallate-conductive polymer composite overlying the current collector. The transition metal hexacyanometallate-conductive polymer includes a AXM1YM2Z(CN)N.MH2O material, where A may be alkali metal ions, alkaline earth metal ions, ammonium ions, or combinations thereof, and M1 and M2 are transition metal ions. The transition metal hexacyanometallate-conductive polymer composite also includes a conductive polymer material. In one aspect, the conductive polymer material is polyaniline (PANI) or polypyrrole (Ppy). Also presented herein are methods for the fabrication of a TMHCM-CP composite.

Abstract: A transition metal hexacyanometallate (TMHCM)-conductive polymer (CP) composite electrode is provided. The battery electrode is made up of a current collector and a transition metal hexacyanometallate-conductive polymer composite overlying the current collector. The transition metal hexacyanometallate-conductive polymer includes a AXM1YM2Z(CN)N.MH2O material, where A may be alkali metal ions, alkaline earth metal ions, ammonium ions, or combinations thereof, and M1 and M2 are transition metal ions. The transition metal hexacyanometallate-conductive polymer composite also includes a conductive polymer material. In one aspect, the conductive polymer material is polyaniline (PANI) or polypyrrole (Ppy). Also presented herein are methods for the fabrication of a TMHCM-CP composite.

Abstract: An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

Abstract: An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

Abstract: A method of chemical vapor deposition (CVD) of copper films includes preparing a substrate, including forming structures thereon have a barrier metal exposed surface; placing the prepared substrate into a CVD chamber; heating the substrate to a temperature of between about 200° C. and 250° C.; introducing a water flow in a carrier gas for at least one minute; stopping the water flow; and starting the flow of copper precursor.

Abstract: A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Abstract: A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Abstract: An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

Abstract: An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

Abstract: A method of forming a highly adhesive copper thin film on a metal nitride substrate includes preparing a substrate having a metal nitride barrier layer formed on a portion thereof; heating the substrate in a chemical vapor deposition chamber to a temperature of between 160° C. to 250° C. for about one minute and simultaneously introducing a copper precursor into the reaction chamber at a very slow initial flow rate of between less than 0.1 ml/min, and simultaneously providing an initial high wet helium gas flow in the reaction chamber of greater than or equal to 5 sccm; reducing the wet helium gas flow in the reaction chamber to less than 5 sccm; and increasing the flow of copper precursor to between about 0.1 ml/min and 0.6 ml/min.

Abstract: A method of forming a highly adhesive copper thin film on a metal nitride substrate includes preparing a substrate having a metal nitride barrier layer formed on a portion thereof; heating the substrate in a chemical vapor deposition chamber to a temperature of between 160° C. to 250° C. for about one minute and simultaneously introducing a copper precursor into the reaction chamber at a very slow initial flow rate of between less than 0.1 ml/min, and simultaneously providing an initial high wet helium gas flow in the reaction chamber of greater than or equal to 5 sccm; reducing the wet helium gas flow in the reaction chamber to less than 5 sccm; and increasing the flow of copper precursor to between about 0.1 ml/min and 0.6 ml/min.

Abstract: A three-dimensional ferroelectric structure and fabrication method are provided. The ferroelectric capacitor structure permits immediate contact between a noble metal capacitor electrode and a transistor electrode. This direct connection minimizes process steps and electrical resistance between capacitor and transistor. A damascene capacitor electrode formation process makes the task of etching the noble metal less critical. Regardless of whether a noble metal capacitor electrode is used, the damascene formation process permits both larger, and more space efficient, capacitors. Further, the damascene capacitor formation process can be used to simultaneously form electrical interlevel interconnections to the transistor drain. Another variation of the invention provides for a dual damascene version of the ferroelectric capacitor.

Abstract: A three-dimensional ferroelectric structure and fabrication method are provided. The ferroelectric capacitor structure permits immediate contact between a noble metal capacitor electrode and a transistor electrode. This direct connection minimizes process steps and electrical resistance between capacitor and transistor. A damascene capacitor electrode formation process makes the task of etching the noble metal less critical. Regardless of whether a noble metal capacitor electrode is used, the damascene formation process permits both larger, and more space efficient, capacitors. Further, the damascene capacitor formation process can be used to simultaneously form electrical interlevel interconnections to the transistor drain. Another variation of the invention provides for a dual damascene version of the ferroelectric capacitor.

Abstract: A method of producing a low-k interconnect dielectric material, using PECVD processes and readily available precursors to produce carbon-doped silicon oxide (SiOC). SiOC dielectric materials are produced using conventional silane based gas precursors, of silane and nitrous oxide, along with hydrocarbon gas. The use of methane and acetylene in combination with silane based gas precursors is provided. Methane produces network terminating species, specifically methyl, which replaces oxygen in an Si—O bond within a silicon dioxide network. This increases the volume, reduces the density and the dielectric constant of the material. Acetylene acts as a possible source of carbon and as a modifier, reducing or eliminating undesirable bridging species, such as carbene, or enhancing desireable network terminating species, such as methyl. Following implantation, the material is annealed to reduce the—OH and to potentially further lower the dielectric constant.

Abstract: A method of CMP includes forming a CMP slurry containing cerium oxide; adding a slurry modifier to the slurry, wherein the slurry modifier polishes low structure areas at a substantially zero rate and polishes high structure areas at a rate approximating a blanket polishing rate; and polishing a structure using the modifier-contained slurry.

Abstract: A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Abstract: A method of forming conducting diffusion barriers is provided. The method produces substantially amorphous conducting diffusion barriers by depositing materials with varying ratios of elements throughout the diffusion barrier. Diffusion barriers of metal nitride, metal silicon nitride, are deposited using CVD, PECVD, or ALCVD, by depositing material with a first ratio of elements and then depositing substantially identical material with a different ratio of elements. The actual elements used are the same, but the ratio is changed. By changing the ratio of the elements within the same diffusion barrier, density variations are produced, and the material is not able to form undesirable polycrystalline structures.

Abstract: A method of fabricating a MOSFET includes: depositing an oxide layer on the planarized substrate; forming a silicon nitride island above a gate region in the substrate; building an oxide sidewall about the nitride island; forming a source region and a drain region in the substrate; removing the silicon nitride island, thereby leaving a void over the gate region; forming a gate dielectric over the gate region in the void; filling the void and the areas over the source region and drain region; planarizing the upper surface of the structure by chemical mechanical polishing; depositing a metal layer on the upper surface of the structure; and metallizing the structure to form electrodes in electrical contact with the source region, the gate region, and the drain region.

Abstract: A metal(hfac), alkene ligand precursor has been provided. The alkene ligand includes double bonded carbon atoms, with first and second bonds to the first carbon atom, and third and fourth bonds to the second carbon atom. The first, second, third, and fourth bonds are selected from a the group consisting of H, C.sub.1 to C.sub.8 alkyl, C.sub.1 to C.sub.8 haloalkyl, and C.sub.1 to C.sub.8 alkoxyl. As a general class, these precursors are capable of high metal deposition rates and high volatility, despite being stable in the liquid phase at low temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described alkene ligand class of metal precursors.

Abstract: A Cu(hfac) allyl-derived ligand precursor has been provided. The ligand includes group consisting of alkyl, phenyl, trialkylsilane, trialkoxylsilane, halodialkylsilane, dihaloalkylsilane, trihalosilane, triphenylsilane, alkoxyl, halogen, chloroformate, cynanide, cycloalkyl, cycloalkylamine, alkyl ether, isocyanate, and pentafluorobenzene. Examples of the allyl-derived ligand precursors have proved to be stable at room temperatures, and sufficiently volatile at higher temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described precursors, including a Cu(hfac)(allyltrimethylsilane) precursor.